ILC6377 データシートの表示（PDF） - Fairchild Semiconductor

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ILC6377

0.5A, 300kHz, SO-8 PWM/PFM Step Down Converter with Shutdown

Fairchild Semiconductor 

ILC6376/77

VIN

S/D

EXT1

*CIN +

1

8

2 ILC6376/77 7

3

6

(TOP VIEW)

4

5

CSS

SD1

L

+

CL

VOUT

Fig.2 1Amp output current application

using external MOSFET

The EXT1 and EXT2 pins are provided so as to drive exter-

nal transistors; thus allowing design flexibility. The EXT1

output drive signal has the same timing as the gate drive to

the internal P-channel MOSFET i.e. EXT1 output is low as

long as the internal MOSFET is on. Both EXT1 and EXT2

pins are capable of driving 1000pF gate capacitance. For

example, a high output current application circuit using an

external P-channel MOSFET is shown in figure 2.

To pin 8

6 CFB

5

VOUT

RFB1

RFB2

RFB1 + RFB2 < 2MW

1

CFB chosen so that 1kHz < 2 x π x CFB x RFB1

< 20kHz

Fig.4 Adjustable output using ILC6376/77SOADJ

(Note: rest of circuit is same as Fig.1)

Adjustable Output (ILC6376/77SOADJ)

For adjustable output voltage ILC6376/77SOADJ should be

used. All connections to the ILC6376/77SOADJ are the

same as ILC6376/77SOXX, except for the feedback voltage

divider network shown in figure 4. The output voltage,

VOUT, can be calculated from the following equation:

VOUT = VFB (1 + RFB1/RFB2), where VFB is approximately

1V and RFB1 + RFB2 < 2MΩ

CBST

2200pF

SD2

MBR0520L

Schottky

1

8

2 ILC6376/77 7

3

6

(TOP VIEW)

4

5

Voltage between Vin and

P_BST must be less than 10V.

Figure 3. P-Channel Negative

Boost Circuit

P-Channel Boost Circuit

The ILC6376/77 includes a unique P-Channel MOSFET

architecture with built-in charge pump to maintain low on-

resistance even at low input voltages. As shown in figure 3, a

2200pF ceramic capacitor and a schottky diode (MBR0520L

or equivalent) allows the gate voltage of the internal P-Chan-

nel MOSFET to be driven negative; thus reducing the switch

on-resistance. This technique can be employed to increase

efficiency at low input voltages and high output currents.

Note that the voltage between VIN and P_BST should not

exceed 10V, otherwise damage to the device may occur. For

high input voltage applications the schottky diode should be

replaced by a low voltage zener diode so that the P_BST pin

is clamped to a safe negative voltage.

The feedback compensation capacitor should be chosen such

that the pole frequency f is between 1kHz and 20kHz:

1

1kHz < 2 x π x CFB x RFB1 < 20kHz

The pole frequency should generally be set at 5kHz. The

value of CFB calculated from the above equation may require

some adjustment depending on the output inductor (L) and

output capacitor (CL) values chosen.

Example for 3V output:

RFB1 = 400kΩ

RFB2 = 200kΩ

CFB = 100pF

PC Board Layout

As with all switching DC-DC converter designs, good PC

board layout is critical for optimum performance. The heavy

lines indicated in figure 1 schematic should be wide

printed circuit board traces and should be kept as short

as is practical. A large ground plane with as much copper

area as is allowable should be used. All external components

should be mounted as close to the IC as possible. For

ILC6376/77SOADJ, the feedback resistors and their associ-

ated wiring should be kept away from the inductor location

and the vicinity of inductive flux.

©2001 Fairchild Semiconductor Corporation

7

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