IN24LC02B データシートの表示（PDF） - Integral Corp.

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IN24LC02B

2K 2.5V CMOS Serial EEPROMs

Integral Corp. 

IN24LC02B

Note: The IN24LC02B does not generate any acknowledge bits if an internal programming cycle is in

progress

The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse

in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an

end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked

out of the slave. In this case, the slave must leave the data line HIGH to enable the master to

generate the STOP condition.

Figure 4. Data Transfer Sequence on the serial bus

BUS CHARACTERISTICS

Slave Address

The IN24LC02B are software-compatible with devices such as 24C01A, 24C02A, 24LC01,

and 24LC02B. A single 24LC02B can be used in place of two 24LC01's,

for example, without any modifications to software.

The "chip select" portion of the control byte becomes a don't care.

After generating a START condition, the bus master transmits the slave address consisting

of a 4-bit device code (1010) for the IN24LC02B, followed by three don't care bits.

The eighth bit of slave address determines if the master device wants to read or write to

the IN24LC02B (see Figure 5).

The IN24LC0 monitors the bus for its corresponding slave address all the time.

It generates an acknowledge bit if the slave address was true and it is not in a programming

mode.

Operation

Read

Write

Control Code

1010

1010

Chip Select

XXX

XXX

R/W

1

0

5

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