IN74AC109 データシートの表示（PDF） - Integral Corp.

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IN74AC109

Dual J-K Flip-Flop with Set and Reset

Integral Corp. 

TECHNICAL DATA

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

IN74AC109

The IN74AC109 is identical in pinout to the

LS/ALS109,HC/HCT109. The device inputs are compatible with

standard CMOS outputs, with pullup resistors, they are compatible

with LS/ALS outputs.

This device consists of two J-K flip-flops with individual set, reset,

and clock inputs. Changes at the inputs are reflected at the outputs with

the next low-to-high transition of the clock. Both Q to Q outputs are

available from each flip-flop.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA; 0.1 µA @ 25°C

• High Noise Immunity Characteristic of CMOS Devices

• Outputs Source/Sink 24 mA

ORDERING INFORMATION

IN74AC109N Plastic

IN74AC109D SOIC

TA = -40° to 85° C for all

packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=VCC

PIN 8 = GND

FUNCTION TABLE

Inputs

Outputs

Set Reset Clock J K Q Q

LH

X XX H L

HL

L

L

X XX L H

X

X X H*

H*

HH

LL L H

HH

H L Toggle

HH

L H No Change

HH

HH H L

HH

L X X No Change

X = Don’t care

*Both outputs will remain high as long as Set and

Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

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