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IN74HC112A データシートの表示(PDF) - IK Semicon Co., Ltd

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IN74HC112A
IKSEMICON
IK Semicon Co., Ltd IKSEMICON
IN74HC112A Datasheet PDF : 6 Pages
1 2 3 4 5 6
IN74HC112A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay , Reset to Q or Q
(Figures 2 and 4)
tPLH, tPHL Maximum Propagation Delay ,Set to Q or Q
(Figures 2 and 4)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
CIN Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C to 85°C 125°C
-55°C
2.0 6.0
4.8
4.0
4.5 30
24
20
6.0 35
28
24
2.0 125 155 190
4.5 25
31
38
6.0 21
26
32
2.0 155 195 235
4.5 31
39
47
6.0 26
33
40
2.0 165 205 250
4.5 33
41
50
6.0 28
35
43
2.0 75
4.5 15
6.0 13
95
110
19
22
16
19
-
10
10
10
Unit
MHz
ns
ns
ns
ns
pF
Power Dissipation Capacitance (Per Flip-Flop)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
35
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to-55°C
85°C
125°C
Unit
tSU
Minimum Setup Time,J or K
2.0
100
to Clock (Figure 3)
4.5
20
6.0
17
125
150
ns
25
30
21
26
th
Minimum Hold Time, Clock
2.0
3
to J or K (Figure 3)
4.5
3
6.0
3
3
3
ns
3
3
3
3
trec
Minimum Recovery Time, Set 2.0
100
or Reset Inactive to Clock
4.5
20
(Figure 2)
6.0
17
125
150
ns
25
30
21
26
tw
Minimum Pulse Width, Clock 2.0
80
(Figure 1)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tw
Minimum Pulse Width, Set or 2.0
80
Reset (Figure 2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall 2.0
Times (Figure 1)
4.5
6.0
1000
500
400
1000
1000
ns
500
500
400
400
Rev. 00

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