INTEL387TMDX データシートの表示（PDF） - Intel

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INTEL387TMDX

Intel387™ DX MATH COPROCESSOR

Intel 

Intel387TM DX MATH COPROCESSOR

2 7 2 EXCEPTIONS

A number of differences exist due to changes in the

IEEE standard and to functional improvements to

the architecture of the Intel387 DX MCP

1 When the overflow or underflow exception is

masked the Intel387 DX MCP differs from the

80287 in rounding when overflow or underflow

occurs The Intel387 DX MCP produces results

that are consistent with the rounding mode

2 When the underflow exception is masked the

Intel387 DX MCP sets its underflow flag only if

there is also a loss of accuracy during denormali-

zation

3 Fewer invalid-operation exceptions due to de-

normal operands because the instructions

FSQRT FDIV FPREM and conversions to BCD

or to integer normalize denormal operands be-

fore proceeding

4 The FSQRT FBSTP and FPREM instructions

may cause underflow because they support de-

normal operands

5 The denormal exception can occur during the

transcendental instructions and the FXTRACT

instruction

6 The denormal exception no longer takes prece-

dence over all other exceptions

7 When the denormal exception is masked the In-

tel387 DX MCP automatically normalizes denor-

mal operands The 8087 80287 performs unnor-

mal arithmetic which might produce an unnor-

mal result

8 When the operand is zero the FXTRACT in-

struction reports a zero-divide exception and

leaves b % in ST(1)

9 The status word has a new bit (SF) that signals

when invalid-operation exceptions are due to

stack underflow or overflow

10 FLD extended precision no longer reports denor-

mal exceptions because the instruction is not

numeric

11 FLD single double precision when the operand

is denormal converts the number to extended

precision and signals the denormalized operand

exception When loading a signaling NaN FLD

single double precision signals an invalid-oper-

and exception

12 The Intel387 DX MCP only generates quiet

NaNs (as on the 80287) however the Intel387

DX MCP distinguishes between quiet NaNs and

signaling NaNs Signaling NaNs trigger excep-

tions when they are used as operands quiet

NaNs do not (except for FCOM FIST and

FBSTP which also raise IE for quiet NaNs)

13 When stack overflow occurs during FPTAN and

overflow is masked both ST(0) and ST(1) con-

tain quiet NaNs The 80287 8087 leaves the

original operand in ST(1) intact

14 When the scaling factor is g % the FSCALE

(ST(0) ST(1)) instruction behaves as follows

(ST(0) and ST(1) contain the scaled and scaling

operands respectively)

 FSCALE(0 %) generates the invalid operation

exception

 FSCALE(finite b%) generates zero with the

same sign as the scaled operand

 FSCALE(finite a %) generates % with the

same sign as the scaled operand

The 8087 80287 returns zero in the first case

and raises the invalid-operation exception in the

other cases

15 The Intel387 DX MCP returns signed infinity

zero as the unmasked response to massive

overflow underflow The 8087 and 80287 sup-

port a limited range for the scaling factor within

this range either massive overflow underflow do

not occur or undefined results are produced

3 0 HARDWARE INTERFACE

In the following description of hardware interface

the symbol at the end of a signal name indicates

that the active or asserted state occurs when the

signal is at a low voltage When no is present after

the signal name the signal is asserted when at the

high voltage level

3 1 Signal Description

In the following signal descriptions the Intel387 DX

Math Coprocessor pins are grouped by function as

follows

1 Execution control CPUCLK2 NUMCLK2 CKM

RESETIN

2 MCP handshake PEREQ BUSY ERROR

3 Bus interface pins D31 – D0 W R ADS

READY READYO

4 Chip Port Select STEN NPS1

CMD0

NPS2

5 Power supplies VCC VSS

Table 3 1 lists every pin by its identifier gives a brief

description of its function and lists some of its char-

acteristics All output signals are tristate they leave

floating state only when STEN is active The output

buffers of the bidirectional data pins D31 – D0 are

also tristate they leave floating state only in read

cycles when the MCP is selected (i e when STEN

NPS1 and NPS2 are all active)

Figure 3 1 and Table 3 2 together show the location

of every pin in the pin grid array

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