INTEL387TMDX データシートの表示（PDF） - Intel

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INTEL387TMDX

Intel387™ DX MATH COPROCESSOR

Intel 

CONTENTS

PAGE

FIGURES (Continued)

Figure 3 2 Asynchronous Operation

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Figure 3 3 Intel386TM DX Microprocessor and Intel387TM DX MCP Coprocessor System

Configuration

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Figure 3 4 Bus State Diagram

25

Figure 3 5 Nonpipelined Read and Write Cycles

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Figure 3 6 Fastest Transitions to and from Pipelined Cycles

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Figure 3 7 Pipelined Cycles with Wait States

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Figure 3 8 STEN BUSY and PEREQ Timing Relationship

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Figure 4 0a Typical Output Valid Delay vs Load Capacitance at Max Operating

Temperature

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Figure 4 0b Typical Output Rise Time vs Load Capacitance at Max Operating

Temperature

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Figure 4 1 CPUCLK2 NUMCLK2 Waveform and Measurement Points for Input Output A C

Specifications

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Figure 4 2 Output Signals

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Figure 4 3 Input and I O Signals

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Figure 4 4 RESET Signal

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Figure 4 5 Float from STEN

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Figure 4 6 Other Parameters

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TABLES

Table 2 1 Intel387TM DX MCP Data Type Representation in Memory

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Table 2 2 Condition Code Interpretation

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Table 2 3 Condition Code Interpretation after FPREM and FPREM1 Instructions

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Table 2 4 Condition Code Resulting from Comparison

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Table 2 5 Condition Code Defining Operand Class

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Table 2 6 Intel386TM DX Microprocessor Interrupt Vectors Reserved for MCP

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Table 2 7 Exceptions

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Table 3 1 Intel387TM DX MCP Pin Summary

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Table 3 2 Intel387TM DX MCP Pin Cross-Reference

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Table 3 3 Output Pin Status after Reset

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Table 3 4 Bus Cycles Definition

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Table 4 1 DC Specifications

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Table 4 2a Combinations of Bus Interface and Execution Speeds

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Table 4 2b Timing Requirements of the Execution Unit

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Table 4 2c Timing Requirements of the Bus Interface Unit

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Table 4 3 Other Parameters

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