IP1001LF データシートの表示（PDF） - Unspecified

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IP1001LF

Integrated 10/100/1000 Gigabit Ethernet Transceiver

Unspecified 

IP1001 LF

Data Sheet

Pin no.

39

Label

MAC Interface

GMII

RGMII

RX_CLK RXC

Type Description

MII

RX_CLK O

GMII/ RGMII Receive Clock.

I/F

MDI Description

speed

Gigabit 125Mhz output.

GMII

IP1001 sends out RXD[7:0],

Mode

RXDV and RX_ER at the

rising edge of RX_CLK.

100Mbps 25Mhz output.

IP1001 sends out RXD[3:0],

RXDV and RX_ER at the

rising edge of RX_CLK.

10Mbps 2.5Mhz output.

IP1001 sends out RXD[3:0],

RXDV and RX_ER at the

rising edge of RX_CLK.

Gigabit 125Mhz output.

RGMII

IP1001 sends out RXD[3:0]

Mode

and RX_CTL at both the

rising edge and falling edge

of RXC.

100Mbps 25Mhz output.

IP1001 sends out RXD[3:0]

and RX_CTL at both the

rising edge and falling edge

of RXC.

10Mbps 2.5Mhz output.

IP1001 sends out RXD[3:0]

and RX_CTL at both the

rising edge and falling edge

of RXC.

40

RX_DV RX_CTL RX_DV O

GMII and MII Receive Enable/ RGMII Receive

Control

I/F

GMII

Mode

MDI Description

speed

Gigabit RX_DV indicates the valid

100Mbps data is present on the data

10Mbps bus of RXD. Synchronous to

the rising edge of RX_CLK.

Gigabit RX_CTL indicates a signal

RGMII 100Mbps like RX_DV at the rising edge

Mode

of TXC. A signal like RX_ER

10Mbps is derived by the logical

operation of latched RX_DV

and the value at the falling

edge of RX_CLK

51,50,49,48 RXD[7:4] --

--

O

GMII Receive Data (high nibble)

Please see the pin description of pin 39.

RXD[7:4] share the same pins with

PHY_ADDR[3:4], TXPHASE_SEL, and

RXPHASE_SEL.

9/48

Copyright © 2006, IC Plus Corp.

Dec. 18, 2007

IP1001-DS-R06

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