IP1000ALF-DS-R01 データシートの表示（PDF） - Unspecified

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IP1000ALF-DS-R01

Gigabit Ethernet NIC Single Chip

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2 Function Description

2.1 Physical Layer

2.1.1 Introduction

IP1000A LF

Preliminary Data Sheet

Figure 2-1 : DSP Function Block Diagram

TX_EN

TX_ER

TXD[7:0]

GTX_CLK

TX_CLK

COL

10/100/1000

Transmit

PCS

Balance

FIFO

Echo

Canceller

NEXT

Canceller

Waveshape

Filter

DAC

DRIVER

RX_DV

RX_ER

RXD[7:0]

RX_CLK

CRS

10/100/

1000

Receive

PCS

FFE

De-skew

FIFO

ADC

Gain

Control

Baseline

Wander

Compensation

Hybrid

DFE/VITERBI

Timing

Recovery

10BASE-T

Receiver

DPLL

MDC

MDIO

INT#

Serial Interface

Management

PHY Registers

Auto-Negotiation

TP_MDI[3:0]

With state-of-the-art DSP mixed-mode technology, the physical layer of IP1000A LF is designed to

accomplish low power, high performance, and full integration for 1000BASE-T, 100BASE-TX, and

10BASE-T operation.

The IP1000A LF eastablish a proper link mode with its link partner through Auto-Negotiation process.

Automatic MDI/MDI-X crossover function and wire polarity correction capability ensure robust data

exchange over CAT5 UTP cables. Channel skews among different pairs of the cable are also

automatically adjusted.

2.1.2 Receiver Fucntion

2.1.2.1 Active Hybrid

The IP1000A LF implements an on-chip hybrid to reduce the near-end echo by subtracting the replica of

the transmitted signal from the input signal. This hybrid relieves the precision requirement of ADC and

the digital echo canceller.

2.1.2.2 Analog to Digital Converter (ADC)

The ADC function block converts analog signal to digitized samples at 125MHz. With an advanced

architecture and high linearity, the ADC is able to provide excellent quantization accuracy for subsequent

digital signal processing.

Copyright © 2005, IC Plus Corp.

10/75

July 5, 2005

IP1000A LF-DS-R08

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