INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

4 0 PROTECTED MODE

ARCHITECTURE

The complete capabilities of the Intel386 SX Micro-

processor are unlocked when the processor oper-

ates in Protected Virtual Address Mode (Protected

Mode) Protected Mode vastly increases the linear

address space to four gigabytes (232 bytes) and al-

lows the running of virtual memory programs of al-

most unlimited size (64 terabytes (246 bytes)) In ad-

dition Protected Mode allows the Intel386 SX Micro-

processor to run all of the existing Intel386 DX CPU

(using only 16 megabytes of physical memory)

80286 and 8086 CPU’s software while providing a

sophisticated memory management and a hard-

ware-assisted protection mechanism Protected

Mode allows the use of additional instructions spe-

cially optimized for supporting multitasking operating

systems The base architecture of the Intel386 SX

Microprocessor remains the same the registers in-

structions and addressing modes described in the

previous sections are retained The main difference

between Protected Mode and Real Mode from a

programmer’s viewpoint is the increased address

space and a different addressing mechanism

4 1 Addressing Mechanism

Like Real Mode Protected Mode uses two compo-

nents to form the logical address a 16-bit selector is

used to determine the linear base address of a seg-

ment the base address is added to a 32-bit effective

address to form a 32-bit linear address The linear

address is then either used as a 24-bit physical ad-

dress or if paging is enabled the paging mechanism

maps the 32-bit linear address into a 24-bit physical

address

The difference between the two modes lies in calcu-

lating the base address In Protected Mode the se-

lector is used to specify an index into an operating

system defined table (see Figure 4 1) The table

contains the 32-bit base address of a given seg-

ment The physical address is formed by adding the

base address obtained from the table to the offset

Paging provides an additional memory management

mechanism which operates only in Protected Mode

Paging provides a means of managing the very large

segments of the Intel386 SX Microprocessor as

paging operates beneath segmentation The page

mechanism translates the protected linear address

which comes from the segmentation unit into a

physical address Figure 4 2 shows the complete In-

tel386 SX Microprocessor addressing mechanism

with paging enabled

24

4 2 Segmentation

Segmentation is one method of memory manage-

ment Segmentation provides the basis for protec-

tion Segments are used to encapsulate regions of

memory which have common attributes For exam-

ple all of the code of a given program could be con-

tained in a segment or an operating system table

may reside in a segment All information about each

segment is stored in an 8 byte data structure called

a descriptor All of the descriptors in a system are

contained in descriptor tables which are recognized

by hardware

TERMINOLOGY

The following terms are used throughout the discus-

sion of descriptors privilege levels and protection

PL Privilege Level One of the four hierarchical

privilege levels Level 0 is the most privileged

level and level 3 is the least privileged

RPL Requestor Privilege Level The privilege level

of the original supplier of the selector RPL is

determined by the least two significant bits of

a selector

DPL Descriptor Privilege Level This is the least

privileged level at which a task may access

that descriptor (and the segment associated

with that descriptor) Descriptor Privilege Lev-

el is determined by bits 6 5 in the Access

Right Byte of a descriptor

CPL Current Privilege Level The privilege level at

which a task is currently executing which

equals the privilege level of the code segment

being executed CPL can also be determined

by examining the lowest 2 bits of the CS regis-

ter except for conforming code segments

EPL Effective Privilege Level The effective privi-

lege level is the least privileged of the RPL

and the DPL EPL is the numerical maximum

of RPL and DPL

Task One instance of the execution of a program

Tasks are also referred to as processes

DESCRIPTOR TABLES

The descriptor tables define all of the segments

which are used in a Intel386 SX Microprocessor sys-

tem There are three types of tables which hold de-

scriptors the Global Descriptor Table Local De-

scriptor Table and the Interrupt Descriptor Table All

of the tables are variable length memory arrays and

can vary in size from 8 bytes to 64K bytes Each

table can hold up to 8192 8-byte descriptors The

upper 13 bits of a selector are used as an index into

the descriptor table The tables have registers asso-

ciated with them which hold the 32-bit linear base

address and the 16-bit limit of each table

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