INTEL386 データシートの表示（PDF） - Intel

部品番号

コンポーネント説明

メーカー

INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

INTRODUCTION

The Intel386 SX Microprocessor is 100% object

code compatible with the Intel386 DX 286 and 8086

microprocessors Systems based on the Intel386 SX

CPU can access the world’s largest existing micro-

computer software base including the growing 32-

bit software base

Instruction pipelining and a high performance ALU

ensure short average instruction execution times

and high system throughput

The integrated memory management unit (MMU) in-

cludes an address translation cache multi-tasking

hardware and a four-level hardware-enforced pro-

tection mechanism to support operating systems

The virtual machine capability of the Intel386 SX

CPU allows simultaneous execution of applications

from multiple operating systems

The Intel386 SX CPU offers on-chip testability and

debugging features Four breakpoint registers allow

conditional or unconditional breakpoint traps on

code execution or data accesses for powerful de-

bugging of even ROM-based systems Other testa-

bility features include self-test tri-state of output

buffers and direct access to the page translation

cache

The Low Power Intel386 SX CPU brings the benefits

of the Intel386 Microprocessor 32-bit architecture to

Laptop and Notebook personal computer applica-

tions With its power saving 2 MHz sleep-mode and

extended functional temperature range of 0 C to

100 C TCASE the Lower Power Intel386 SX CPU

specifically satisfies the power consumption and

heat dissipation requirements of today’s small form

factor computers

2 0 BASE ARCHITECTURE

The Intel386 SX Microprocessor consists of a cen-

tral processing unit a memory management unit and

a bus interface

The central processing unit consists of the execu-

tion unit and the instruction unit The execution unit

contains the eight 32-bit general purpose registers

which are used for both address calculation and

data operations and a 64-bit barrel shifter used to

speed shift rotate multiply and divide operations

The instruction unit decodes the instruction opcodes

and stores them in the decoded instruction queue

for immediate use by the execution unit

The memory management unit (MMU) consists of a

segmentation unit and a paging unit Segmentation

allows the managing of the logical address space by

providing an extra addressing component one that

allows easy code and data relocatability and effi-

cient sharing The paging mechanism operates be-

neath and is transparent to the segmentation pro-

cess to allow management of the physical address

space

The segmentation unit provides four levels of pro-

tection for isolating and protecting applications and

the operating system from each other The hardware

enforced protection allows the design of systems

with a high degree of integrity

The Intel386 SX Microprocessor has two modes of

operation Real Address Mode (Real Mode) and

Protected Virtual Address Mode (Protected Mode)

In Real Mode the Intel386 SX Microprocessor oper-

ates as a very fast 8086 but with 32-bit extensions if

desired Real Mode is required primarily to set up the

processor for Protected Mode operation

Within Protected Mode software can perform a task

switch to enter into tasks designated as Virtual 8086

Mode tasks Each such task behaves with 8086 se-

mantics thus allowing 8086 software (an application

program or an entire operating system) to execute

The Virtual 8086 tasks can be isolated and protect-

ed from one another and the host Intel386 SX Micro-

processor operating system by use of paging

Finally to facilitate system hardware designs the

Intel386 SX Microprocessor bus interface offers ad-

dress pipelining and direct Byte Enable signals for

each byte of the data bus

2 1 Register Set

The Intel386 SX Microprocessor has thirty-four reg-

isters as shown in Figure 2-1 These registers are

grouped into the following seven categories

General Purpose Registers The eight 32-bit gen-

eral purpose registers are used to contain arithmetic

and logical operands Four of these (EAX EBX

ECX and EDX) can be used either in their entirety as

32-bit registers as 16-bit registers or split into pairs

of separate 8-bit registers

6

Share Link: