HY57V658020BTC-7I データシートの表示（PDF） - Hynix Semiconductor

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HY57V658020BTC-7I

4Mbit x 2 bank x 8 SDRAM, LVTTL, 100MHz

Hynix Semiconductor 

HY57V658020B

4 Banks x 2M x 8Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low

power consumption and extended temperature range. HY57V658020B is organized as 4banks of 2,097,152x8.

HY57V658020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

• Single 3.3±0.3V power supply

• All device pins are compatible with LVTTL interface

• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

• All inputs and outputs referenced to positive edge of sys-

tem clock

• Data mask function by DQM

• Internal four banks operation

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

HY57V658020BTC-7I

HY57V658020BTC-75I

HY57V658020BTC-10SI

Clock Frequency

143MHz

133MHz

100MHz

Power

Organization

Interface

Package

Normal

Power

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 0.2/Nov. 01

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