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HY57V658020BTC-75I データシートの表示(PDF) - Hynix Semiconductor
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コンポーネント説明
メーカー
HY57V658020BTC-75I
4Mbit x 2 bank x 8 SDRAM, LVTTL, 100MHz
Hynix Semiconductor
HY57V658020BTC-75I Datasheet PDF : 11 Pages
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HY57V658020B
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Parameter
CAS Latency = 3
System Clock Cycle Time
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
CAS Latency = 3
Access Time From Clock
CAS Latency = 2
Data-Out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency = 3
CAS Latency = 2
Symbol
t
CK3
t
CK2
t
CHW
t
CLW
t
AC3
t
AC2
t
OH
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CS
t
CH
t
OLZ
t
OHZ3
t
OHZ2
-7I
Min
Max
7
1000
10
2.5
-
2.5
-
-
5.4
-
6
2.5
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
2.7
5.4
3
6
-75I
Min
Max
7.5
1000
10
2.5
-
2.5
-
-
5.4
-
6
2.5
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
-
5.4
-
6
-10SI
Min
Max
10
1000
12
3
-
3
-
-
6
-
6
2.5
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
-
6
-
6
Unit Note
ns
ns
ns
1
ns
1
ns
2
ns
ns
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
ns
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.2/Nov. 01
7
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