IS24C01B-2GI データシートの表示（PDF） - Integrated Silicon Solution

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IS24C01B-2GI

1K-bit/2K-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C01B IS24C02B

PIN CONFIGURATION

8-Pin DIP, SOIC, TSSOP

8-pad DFN

ISSI ®

A0 1

A1 2

A2 3

GND 4

8 VCC

7 WP

6 SCL

5 SDA

A0 1

A1 2

A2 3

GND 4

8 VCC

7 WP

6 SCL

5 SDA

(Top View)

PIN DESCRIPTIONS

A0-A2

SDA

SCL

WP

Vcc

GND

Address Inputs

Serial Address/Data I/O

Serial Clock Input

Write Protect Input

Power Supply

Ground

SCL

This input clock pin is used to synchronize the data transfer

to and from the device.

SDA

The SDA is a Bi-directional pin used to transfer addresses and

data into and out of the device. The SDA pin is an open drain

output and can be wire-Or'ed with other open drain or open

collector outputs. The SDA bus requires a pullup resistor to

Vcc.

A0, A1, A2

The A0, A1 and A2 are the device address inputs. The

IS24C01B/02B uses the A0, A1, and A2 for hardware addressing

and a total of 8 devices may be used on a single bus system.

When the A0, A1, or A2 inputs are left floating, the input

internally defaults to zero.

WP

WP is the Write Protect pin. If the WP pin is tied to VCC on the

EEPROM, the entire array becomes Write Protected (Read

only). When WP is tied to GND or left floating normal read/

write operations are allowed to the device.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

3

Rev. A

04/12/06

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