IS24C02D データシートの表示（PDF） - Integrated Silicon Solution

部品番号

コンポーネント説明

メーカー

IS24C02D

2-WIRE (I2C) 2K-bit Automotive SERIAL EEPROM

Integrated Silicon Solution 

IS24C02D

The Bus Protocol:

– Data transfer may be initiated only when the bus is not

busy

– During a data transfer, the SDA line must remain stable

whenever the SCL line is high.  Any changes in the SDA

line while the SCL line is high will be interpreted as a

Start or Stop condition.

The state of the SDA line represents valid data after a Start

condition. The SDA line must be stable for the duration of

the High period of the clock signal.  The data on the SDA

line may be changed during the Low period of the clock

signal.  There is one clock pulse per bit of data.  Each data

transfer is initiated with a Start condition and terminated

with a Stop condition.

Start Condition

The Start condition precedes all commands to the device

and is defined as a High to Low transition of SDA when

SCL is High.  The IS24C02D monitors the SDA and SCL

lines and will not respond until the Start condition is met.

Stop Condition

The Stop condition is defined as a Low to High transition

of SDA when SCL is High. All operations must end with

a Stop condition.

Acknowledge (ACK)

After a successful data transfer, each receiving device is

required to generate an ACK.  The Acknowledging device

pulls down the SDA line.

Reset

The IS24C02D contains a reset function in case the

2-wire bus transmission is accidentally interrupted (eg. a

power loss), or needs to be terminated mid-stream. The

reset is caused when the Master device creates a Start

condition. To do this, it may be necessary for the Master

device to monitor the SDA line while cycling the SCL up

to nine times. (For each clock signal transition to High,

the Master checks for a High level on SDA.)

Standby Mode

Power consumption is reduced in standby mode. The

IS24C02D will enter standby mode: a) At Power-up, and

remain in it until SCL or SDA toggles; b) Following the Stop

signal if no write operation is initiated; or c) Following any

internal write operation.

DEVICE ADDRESSING

The Master begins a transmission by sending a Start

condition.  The Master then sends the address of the

particular Slave devices it is requesting. The Slave device

(Fig. 5) address is 8 bits.

The four most significant bits of the Slave device address

are fixed as 1010 for normal read/write operations, and

0110 for permanent write-protection operations.

This device has three address bits (A1, A2, and A0) that

allow up to eight IS24C02D devices to share the 2-wire

bus. Upon receiving the Slave address, the device

compares the three address bits with the hardwired

A2, A1, and A0 input pins to determine if it is the

appropriate Slave. If any of the A2 - A0 pins is neither

biased to High nor Low, internal circuitry defaults the

value to Low.

The last bit of the Slave address specifies whether a Read

or Write operation is to be performed. When this bit is set

to 1, a Read operation is selected, and when set to 0, a

Write operation is selected.

After the Master transmits the Start condition and Slave

address byte (Fig. 5), the appropriate 2-wire Slave (eg.

IS24C02D) will respond with ACK on the SDA line. The

Slave will pull down the SDA on the ninth clock cycle,

signaling that it received the eight bits of data. The

selected IS24C02D then prepares for a Read or Write

operation by monitoring the bus.

6

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

07/27/09

Share Link: