IS24C32A データシートの表示（PDF） - Integrated Silicon Solution

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IS24C32A

64K-bit/32K-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C32A/B

IS24C64A/B

FUNCTIONAL BLOCK DIAGRAM

Vcc 8

SDA 5

SCL 6

WP 7

A0 1

A1 2

A2 3

SLAVE ADDRESS

REGISTER &

COMPARATOR

CONTROL

LOGIC

WORD ADDRESS

COUNTER

GND 4

ACK

nMOS

ISSI ®

HIGH VOLTAGE

GENERATOR,

TIMING & CONTROL

EEPROM

ARRAY

Y

DECODER

Clock

DI/O

> DATA

REGISTER

PIN DESCRIPTIONS

A0-A2

SDA

SCL

WP

Vcc

GND

Address Inputs

Serial Address/Data I/O

Serial Clock Input

Write Protect Input

Power Supply

Ground

SCL

This input clock pin is used to synchronize the data

transfer to and from the device.

SDA

The SDA is a Bi-directional pin used to transfer addresses

and data into and out of the device. The SDA pin is an open

drain output and can be wire-Ored with other open drain

or open collector outputs. The SDA bus requires a pullup

resistor to Vcc.

A0, A1, A2

The A0, A1 and A2 are the device address inputs that are

hardwired or left not connected for hardware compatibility

with the 24C16. When pins are hardwired, as many as eight

32K/64K devices may be addressed on a single bus

system. When the pins are not hardwired, the default values

of A0, A1, and A2 are zero.

PIN CONFIGURATION

8-Pin DIP, SOIC, TSSOP, and MSOP

A0 1

A1 2

A2 3

GND 4

8 VCC

7 WP

6 SCL

5 SDA

WP

WP is the Write Protect pin. The input level determines if all,

partial, or none of the array is protected from modifications.

Write Protection

Array Addresses Protected

WP

GND or floating

Vcc

IS24C32A/64A

None

Entire Array

IS24C32B

None

C00h

-FFFh

IS24C64B

None

1800h

-1FFFh

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/12/06

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