IS23SC4442 データシートの表示（PDF） - Integrated Silicon Solution

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IS23SC4442

256 BYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY

Integrated Silicon Solution 

IS23SC4442

ISSI ®

Functional Description

The IS23SC4442 contains 256 bytes of EEPROM main

memory (see block diagram) and a 32 bit protection

memory. The main memory is byte-wise erased and

written. When the memory is erased, 8 bits of the data

byte are all set to logic 1. When the memory is written, a

data byte can be programmed bit by bit, and it is set to

logic 0 according to the logic between the old and new

data. Generally, updating data includes an erase and

write procedure. When updated, new input data and the

contents of the old data are compared. If none of the 8

bits requires a logic 0 to 1 change, the erase operation

will be skipped. On the contrary, the write operation will

be skipped if no logic 1 to 0 change is necessary. The

write and erase operation takes at least 2.5 ms each.

The first 32 bytes can be protected individually by writing

the corresponding bit in the protection memory. Each

data byte in the address range and its assigned bit in the

protection memory have the same address. Once the

protection bit is written it cannot be erased.

The security memory of IS23SC4442 contains an error

counter (bit 0-bit 2) and 3 bytes reference data. The three

bytes reference data are as a whole called programmable

security code (PSC). After power on, except for the

PSC, the whole memory can always be read. The error

counter can always be written. After three successive

unsuccessful PSC verifications, the error counter will

block the chip, and write and erase operation to the

memory will be forbidden.

TRANSMISSION PROTOCOL

Transmission Mode

The transmission protocol is a two-wire link protocol

between the interface device IFD and IC. The protocol

type is "S = 10". All data changes on I/O are triggered by

the falling edge on CLK.

The transmission protocol is composed of the following

four modes:

– Reset and answer- to-reset

– Command mode

– Data output mode

– Processing mode

Reset and Answer-To-Reset

According to IS07816-3, Answer-To-Reset takes place

during operation. The reset can be implemented at any

time. During reset, the address counter is set to zero.

When RST is set from high level to low level, the lowest

bit of the first byte is read on the I/O. Under continuous

31 clock pulses, the contents of the first 4 byte EEPROM

addresses can be read out. The 33rd clock pulse sets

the I/O to high impedance. During Answer-To-Reset, any

start and stop condition is ignored.

Vcc

RST

CLK

I/O

1

2

3

31

32

IC sets I/O high

impedance

1

2

3

Figure: Reset and Answer-To-Reset

31

32

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

5

Rev. 00B

08/01/03

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