IS42S16800A1-7TL データシートの表示（PDF） - Integrated Silicon Solution

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IS42S16800A1-7TL

8Meg x 16 128-MBIT SYNCHRONOUS DRAM

Integrated Silicon Solution 

IS42S16800A1

ISSI ®

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance

state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the

write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ

bus.

Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

DQM

DQM high for CAS latency = 2 only.

Required to mask first bit of READ data.

COMMAND NOP

READ A

WRITE A

NOP

NOP

NOP

CAS latency = 2

tCK2, DQs

CAS latency = 3

tCK3, DQs

: “H” or “L”

DIN A0

DIN A1

DIN A2

DIN A3

DIN A0

DIN A1

DIN A2

DIN A3

NOP

NOP

NOP

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

11

Rev. 00B

©

05/01/06

N

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