IS61C64AL データシートの表示（PDF） - Integrated Silicon Solution
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IS61C64AL Datasheet PDF : 13 Pages
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IS61C64AL
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-10 ns
-12 ns
Min. Max
Min. Max.
Unit
1
tWC
Write Cycle Time
10
—
12 —
ns
tSCS
CE to Write End
9
—
10 —
ns
tAW
Address Setup Time
9
—
10 —
ns
2
to Write End
tHA
Address Hold
0
—
0—
ns
from Write End
tSA
Address Setup Time
0
—
0—
ns
3
tPWE1
WE Pulse Width (OE LOW)
9
—
9—
ns
tPWE2
WE Pulse Width (OE HIGH)
8
—
8—
ns
tSD
Data Setup to Write End
7
—
7—
ns
4
tHD
Data Hold from Write End
0
—
0—
ns
tHZWE(2)
WE LOW to High-Z Output
—
6
—6
ns
tLZWE(2)
WE HIGH to Low-Z Output
0
—
0—
ns
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
6
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
7
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
8
t WC
ADDRESS
CE
WE
DOUT
DIN
t SA
VALID ADDRESS
t SCS
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
9
10
11
CE_WR1.eps
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/16/06
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