IS63LV1024 データシートの表示（PDF） - Integrated Silicon Solution

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IS63LV1024

128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

Integrated Silicon Solution 

IS63LV1024

IS63LV1024L

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol

tWC

tSCE

tAW

tHA

tSA

tPWE1(1)

tPWE2(2)

tSD

tHD

tHZWE(2)

tLZWE(2)

Parameter

Write Cycle Time

CE to Write End

Address Setup Time to

Write End

Address Hold from

Write End

Address Setup Time

WE Pulse Width (OE High)

WE Pulse Width (OE Low)

Data Setup to Write End

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

-8 ns

-10 ns

-12 ns

Min. Max.

Min. Max.

Min. Max.

Unit

8—

10 —

12 —

ns

7—

7—

8—

ns

8—

8—

8—

ns

0—

0—

0—

ns

0—

0—

0—

ns

7—

7—

8—

ns

8—

10 —

12 —

ns

5—

5—

6—

ns

0—

0—

0—

ns

—4

—5

—6

ns

3—

3—

3—

ns

Notes:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of

the signal that terminates the Write.

AC WAVEFORMS

WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)

ADDRESS

CE

WE

DOUT

DIN

t SA

t WC

VALID ADDRESS

t SCE

t HA

DATA UNDEFINED

t AW

t PWE1

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. I

1/26/07

CE_WR1.eps

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