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ISL29043IROMZ-EVALZ データシートの表示(PDF) - Intersil

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ISL29043IROMZ-EVALZ Datasheet PDF : 16 Pages
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ISL29043
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499k1% tolerance
(Note 11). (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
(Note 7) TYP (Note 7) UNIT
tHD:STA
Hold Time (Repeated) START Condition
After this period, the first clock pulse is
600
ns
generated.
tLOW
LOW Period of the SCL Clock
Measured at the 30% of VDD crossing.
tHIGH
HIGH period of the SCL Clock
tSU:STA
Set-up Time for a Repeated START Condition
tHD:DAT
Data Hold Time
tSU:DAT
Data Set-up Time
tR
Rise Time of both SDA and SCL Signals
(Note 12)
tF
Fall Time of both SDA and SCL Signals
(Note 12)
tSU:STO
Set-up Time for STOP Condition
tBUF
Bus Free Time Between a STOP and START Condition
Cb
Capacitive Load for Each Bus Line
Rpull-up
SDA and SCL System Bus Pull-up Resistor
Maximum is determined by tR and tF
tVD;DAT
Data Valid Time
tVD:ACK
Data Valid Acknowledge Time
VnL
Noise Margin at the Low Level
VnH
Noise Margin at the High Level
NOTES:
11. All parameters in I2C Electrical Specifications table are guaranteed by design and simulation.
12. Cb is the capacitance of the bus in pF.
1300
600
600
30
100
20 + 0.1xCb
20 + 0.1xCb
600
1300
1
0.1VDD
0.2VDD
ns
ns
ns
ns
ns
ns
ns
ns
ns
400 pF
kΩ
0.9 µs
0.9 µs
V
V
FIGURE 3. I2C TIMING DIAGRAM
5
FN7935.0
February 9, 2012

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