NX25F080A-3TI-R データシートの表示（PDF） - NexFlash -> Winbond Electronics

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NX25F080A-3TI-R

8M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE

NexFlash -> Winbond Electronics 

NX25F080A

FUNCTIONAL OVERVIEW

An architectural block diagram of the NX25F080A is shown

in Figure 2. Key elements of the architecture include:

• SPI Interface and Command Set Logic

• Serial Flash Memory Array

• Serial SRAM and Program Buffer

• Write Protection Logic

• Configuration and Status Registers

• Device Information Sector

DEVICE INFORMATION SECTOR

(READ ONLY)

WP

HOLD

OR R/B

SCK

CS

SI

SO

WRITE CONTROL

LOGIC

HOLD OR

READ/BUSY

LOGIC

8 MEGABIT

SERIAL FLASH MEMORY ARRAY

16

2048 BYTE-ADDRESSABLE

SECTORS OF 536 BYTES EACH

CONFIGURATION

REGISTER

STATUS

REGISTER

SPI

COMMAND

AND

CONTROL

LOGIC

HIGH-VOLTAGE

GENERATORS

SECTOR-ADDRESS

LATCH

DATA

BYTE-ADDRESS

LATCH/COUNTER

4288

PROGRAM BUFFER

(536 BYTES)

4288

10

8

SRAM

(536 BYTES)

8

8

COLUMN DECODE, SENSE AMP LATCH

AND DATA COMPARE LOGIC

9

Figure 2. NX25F080A Architectural Block Diagram

2

NexFlash Technologies, Inc.

PRELIMINARY NXSF005C-0699

06/11/99 ©

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