TDA9873H データシートの表示（PDF） - Philips Electronics
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TDA9873H Datasheet PDF : 40 Pages
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Philips Semiconductors
Multistandard dual carrier stereo sound decoder
Product specification
TDA9873H
In the following dematrix, the modes stereo, mono and
dual are processed for the different standards. The 6 dB
level difference between B/G and M standard is
automatically compensated in the dematrix, therefore no
further level adaption is needed.
De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
The time constant is automatically switched to 50 µs or
75 µs according to the chosen standard.
Due to some frequency response peaking of the
FM demodulation, compensation is necessary. This is
done by having a slightly larger time constant for the
de-emphasis.
All other settings such as AF switch, stereo channel
adjustment values or default corrections have to be
controlled via the I2C-bus depending on the identification
or user definition.
AF switch
The circuit incorporates a single stereo and mono
AF output. Using rail-to-rail operational amplifiers, the
clipping level is set to 1.4 V (RMS) for VCC = 5 V.
As well as the internal stereo decoder output signal, one
external stereo and one mono input can be switched to the
AF outputs. Both the mono and stereo outputs can be
switched independent of the internal or external sources
(see Tables 13 and 25). Fig.6 shows the switch
configurations.
A nominal gain of 0 dB for the signals from the external
inputs to the outputs is built-in.
Stereo/dual sound identification
The pilot signal is fed to the input of a NBPLL. The PLL
circuit generates the synchronized pilot carrier. This carrier
is used for the synchronous AM demodulation to get the
low-pass filtered identification signal.
A Schmitt trigger circuit performs pulse shaping of the
identification signal when the signal level is higher than the
Schmitt trigger threshold. For smaller signal levels there is
no AC output signal, thus protecting against
mis-identification caused by spurious signal components.
The identification stages consist of two digital PLL circuits
and digital integrators to generate the stereo or dual sound
identification bits, which can be read out via the I2C-bus.
A 4 MHz crystal oscillator provides the reference clock
frequency. The corresponding detection bandwidth is
larger than ±50 Hz for the pilot carrier signal, so that
fpilot variations from the transmitter can be tracked in the
event of missing synchronization with the horizontal
frequency fH. However, the detection bandwidth for the
identification signal is limited to approximately ±1 Hz for
high identification reliability.
I2C-bus transceiver
The TDA9873H is microcontroller controlled via a 2-wire
I2C-bus.
Two wires, serial data (SDA) and serial clock (SCL) carry
information between the devices connected to the bus.
The TDA9873H has an I2C-bus slave transceiver with
auto-increment.
To avoid conflicts in applications with other ICs providing
similar or complementary functions, two slave addresses
are available, selected on the pin MAD. A slave address is
sent from the master to the slave receiver.
In the TV sound processor family several devices are
available. To identify the TDA9873H device, the master
sends a slave address with R/W bit = 0. The slave then
generates an acknowledge and the master sends the data
subaddress 254 to the slave, followed by an acknowledge
from the slave to the master. The master then sends the
slave address with R/W bit = 1. The slave then transmits
the device identification code 80H to the master, followed
by an acknowledge NOT and a STOP condition generated
by the master.
Control ports
Two digital open-collector output ports P1 and P2 provide
external switching functions in the receiver front-end or
IF demodulators. The ports are controlled by the I2C-bus
(see Tables 22 and 23) and are freely programmable.
2000 Apr 04
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