ISL85402(2011) データシートの表示（PDF） - Intersil

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ISL85402
(Rev.:2011)

2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

Intersil 

Pin Configuration

ISL85402

ISL85402

(20 LD QFN)

TOP VIEW

20 19 18 17 16

EN 1

FS 2

SS 3

FB 4

COMP 5

Therm2al1Pad

P2A1 D

6

7

8

9 10

15 BOOT

14 PGND

13 LGATE

12 SYNC

11 EXT_BOOST

Functional Pin Descriptions

PIN NAME

EN

FS

SS

FB

COMP

ILIMIT

MODE

PGOOD

PHASE

EXT_BOOST

PIN #

DESCRIPTION

1

The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW. Range: 0V to

5.5V.

2

To connect this pin to VCC, or GND, or left open will force the IC to have 500kHz switching frequency. The oscillator switching

frequency can also be programmed by adjusting the resistor from this pin to GND.

3

Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of

the converter. Also this pin can be used to track a ramp on this pin.

This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from VOUT

4

to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and

the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored

for overvoltage events.

5 Output of the voltage feedback error amplifier.

6

Programmable current limit pin. With this pin connected to VCC pin, or to GND, or left open, the current limiting threshold is the set

to default 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.

Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode when

7 the peak inductor current is below the default threshold 700mA. The current boundary threshold between PFM and PWM can also

be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on page 12.

8

9, 10

PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV or UV)

or EN pin pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (VO > 90%).

These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected the source of the

high-side N-channel MOSFET.

This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the

controller will detect the voltage on this pin, if voltage on this pin is below 200mV, the controller is set in

synchronous/non-synchronous buck mode and latch in this state unless VCC is below POR falling threshold; if the voltage on this

pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode the low-side driver

11

output PWM with same duty cycle with upper-side driver to drive the boost switch.

In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold

and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is

disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.

In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “Boost Converter Operation” on page 13 for more

details.

2

FN7640.0

September 29, 2011

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