ISL88011IH544Z データシートの表示（PDF） - Intersil

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ISL88011IH544Z

5-Pin Voltage Supervisors with Adjustable Power-On Reset, Dual Voltage Monitoring or Watchdog Timer Capability

Intersil 

ISL88011, ISL88012, ISL88013, ISL88014, ISL88015

Typical Application Circuits (Continued)

3.3V

VTHL @ 3.09V

VDD

RST

3.3V

100K

PGOOD

50K

VTHH @ 3.6V

10K

ISL8801X-31

3.3V

VDD

RST

VMON

100K

ISL88014 /ISL88015

VOLTAGE OUT OF RANGE = PGOOD LOW

FIGURE 10. OVER/UNDERVOLTAGE MONITOR

Applications: Using the ISL8801XEVAL1

Platform

The ISL8801XEVAL1 board is designed to provide both

immediate functional assessment and flexibility to the user

when evaluating any of the ISL88011 - ISL88015 variants

(illustrated in Figure 11). It consists of two identical banks

which each contain the five different pinouts available in this

product family.

The top bank comes populated for immediate assessment of

functionality and performance. It is populated on the top row

with the VTHVDD = 4.38V variants of the ISL88011, ISL88012

and ISL88013. The bottom row is populated with the

ISL88014 and ISL88015, which monitor positive voltages

>0.6V on the VMON input pin.

The bottom bank is left unpopulated to allow other part options

of the ISL88011, ISL88012 and ISL88013 to be evaluated with

a minimal number of passive components to add. The

RST/MR pull-up resistors are included as well as the

ISL88014 and ISL88015 since these ICs have no voltage

variants.

During power-up, the ISL88011 - ISL88015 supervisors will

assert reset once VDD reaches at least 1V. Thereafter, the

ISL88011, ISL88012 and ISL88013 will release the reset once

the VDD supply stays above 4.38V for the nominal tPOR

period. The ISL88012, ISL88014 and ISL88015’s VMON input

pins are biased to trip at 10.7V, 1.93V and 1.2V respectively.

Note that because the ISL88012 is a dual voltage supervisor,

both of the respective minimum thresholds for the VDD and

VMON inputs must be met before reset is released.

All of the parts have the TwinPinTM RST/MR, which combines

the active-low reset output with a manual reset input. The

push-button can be tested by simply driving this to <100mV

above ground for at least 1µs.

For the ISL88011 and ISL88014, the POR timeout delay tPOR

can be increased from the nominal 250ms by connecting a

capacitor to the CPOR pin. A comparison can be made

between the two as the ISL88014 has a 22pF capacitor on its

CPOR pin while the ISL88011 CPOR is left open.

The ISL88013 and ISL88015 have a WDI input pin, which is

connects to a microprocessor or microcontroller. This input

needs to be periodically toggled within 1sec to prevent the

supervisor from asserting reset. The WDI test point on the

ISL8801XEVAL1 board provides easy access to this input.

Multiple IC configurations as shown in Figures 6 through 10

are easy to evaluate with this platform as each bank is

isolated from the other, thereby making VDD voltages and

GND references indepedent of each other.

SPECIAL CONSIDERATIONS:

Using good decoupling practices will prevent transients from

causing unwanted resets (i.e. due to switching noises and

short duration droops in the supply voltage).

When using the CPOR pin, avoid stray capacitance during

layout as much as possible in order to minimize its effect on

the tPOR timing.

9

FN8093.0

February 13, 2006

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