ISL88011IH546Z-TK データシートの表示（PDF） - Intersil
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ISL88011IH546Z-TK Datasheet PDF : 13 Pages
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ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
Power-On Reset (POR)
Applying at least 1V to the VDD pin activates a POR circuit
which asserts reset (i.e., RST goes HIGH while RST goes
LOW). The reset signals remain asserted until the voltage at
VDD and/or VMON rise above the minimum voltage sense
level for time period tPOR. This ensures that the voltages
have stabilized.
These reset signals provide several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
Adjusting POR Timeout via CPOR Pin
On the ISL88011 and ISL88014, users can adjust the
Power-On Reset timeout delay (tPOR) up to many times the
normal tPOR of 250ms. To do this, connect a capacitor
between CPOR and ground (see Figure 3). For example,
connecting a 30pF capacitor to CPOR will increase tPOR
from a typical 250ms to about 2.5s. NOTE: Care should be
taken in PCB layout and capacitor placement in order to
reduce stray capacitance as much as possible, which
lengthens the tPOR timeout period.
CPOR
ISL88011
ISL88014
6
5
4
3
2
1
0
0 10 20 30 40 50 60 70 80
CPOR (pF)
FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR
Manual Reset
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active-low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for 1µs or longer
while the push-button is closed. After MR is released, the
reset outputs remain asserted for tPOR (200ms) and then
released.
VDD
ISL88011
ISL88012
ISL88013
ISL88014
ISL88015
Rpu
RST/MR
PB
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within tWDT (1.6s nominal),
otherwise the reset signal is asserted (see Figure 5).
Internally, the 1.6s timer is cleared by either a reset or by
toggling the WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for start-up.
During this time, a reset cannot be asserted due to the WDI
not being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the
system software to initialize without the burden of dealing
with the Watchdog.
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
9
FN8093.3
August 9, 2011
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