ISL88041 データシートの表示（PDF） - Intersil

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ISL88041

Quad Voltage Monitor

Intersil 

ISL88041

ISL88041 Description and Operation

The ISL88041 is a four voltage detection IC designed to

monitor multiple voltages ≥0.7V. This IC is suitable for

microprocessors or industrial system applications providing

both reset and manual reset functions.

VDD Lock Out

Applying power to the ISL88041 VDD activates a lock out circuit

which disables the reporting function until VDD rises to ~2.6V.

As VDD bias is applied the RST output is held low before

VDD = 1V. If VDD falls below ~2.4V the lock out of monitoring

and reporting functions is invoked.

Low Voltage Monitoring

Once biased to 2.7V the IC continuously monitors and

reports from one to four voltages independently through

external resistor dividers comparing each VMON pin voltage

to a nominal internal 0.635V reference. Once all VMON input

voltages rise above this threshold, the RST output is

immediately deasserted by being released to be pulled high

via its internal 20kΩ (or optional external) pull resistor to VDD

indicating that all the minimum voltage conditions have been

met (see Figure 4). The RST output is open-drain to allow

ORing of signals and interfacing to a range of logic levels.

Once any VMON input falls below its respective user-set

threshold, the RST output is pulled low after the glitch filter

delay (tFIL) as the VMON inputs are designed to reject short

undervoltage transients of approximately 30µs (see

Figure 5). The user can customize the individual rail

undervoltage threshold (VTRIP) by connecting individual

VMON pins to an external resistor divider according to the

Equation 1:

VTRIP= 0.635V(R1 + R2) ⁄ R2

(EQ. 1)

See Figure 8 for a typical application configuration.

Manual Reset

The manual-reset input (MR) allows the user to trigger a reset

by using a push-button switch or by signaling the input low.

Reset is asserted and deasserted immediately upon MR

transitioning through MRVTH, see Figures 6 and 7.

Figure 1 is the operational timing diagram.

Using the ISL88041EVAL1

The ISL88041EVAL1 is the evaluation platform for this

product and illustrates the flexibility and simplicity of

monitoring four separate voltages. The RST output can be

monitored once the VDD, GND, and appropriate 3.3V, 2.5V,

1.8V and 1.2V supply voltage inputs are properly biased as

labeled. A Manual Reset (MR) input is also available for

evaluation.

The circuit as shown in Figures 10 and 11 has resistor

dividers chosen to monitor for an undervoltage threshold

level of 89% of the 4 nominal voltages. Figure 1 illustrates

the expected behavior and Figures 4 through 7 illustrate the

actual IC performance in the ISL88041EVAL1.

VTH

VMON

1V

MR

RST

tRPD

<tFIL

>tFIL

tMR

tMD

FIGURE 1. ISL88041 OPERATIONAL TIMING DIAGRAM

4

FN9229.2

April 29, 2010

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