ISL9012IRCCZ データシートの表示（PDF） - Intersil

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ISL9012IRCCZ

Dual LDO with Low Noise, Low IQ, and High PSRR

Intersil 

ISL9012

Pin Description

PIN #

1

2

3

4

5

6

7

8

9

10

PIN

NAME

VIN

EN1

EN2

CBYP

CPOR

GND

NC

POR

VO2

VO1

TYPE

DESCRIPTION

Analog I/O

Supply Voltage/LDO Input:

Connect a 1μF capacitor to GND.

Low Voltage Compatible LDO-1 Enable.

CMOS Input

Low Voltage Compatible LDO-2 Enable.

CMOS Input

Analog I/O

Reference Bypass Capacitor Pin:

Optionally connect capacitor of value 0.01μF to 1μF between this pin and GND to tune in the

desired noise and PSRR performance.

Analog I/O

POR Delay Setting Capacitor Pin:

Connect a capacitor between this pin and GND to delay the POR output release after LDO-2

output reaches 94% of its specified voltage level (200ms delay per 0.01μF).

Ground

GND is the connection to system ground. Connect to PCB Ground plane.

NC

No Connection.

Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low).

Analog I/O

LDO-2 Output:

Connect capacitor of value 1μF to 10μF to GND (1µF recommended).

Analog I/O

LDO-1 Output:

Connect capacitor of value 1μF to 10μF to GND (1µF recommended).

Typical Application

VIN (2.3-6.5V)

ON

Enable 1

OFF ON

Enable 2

OFF

ISL9012

1

VIN

10

VO1

2

EN1

9

VO2

3

EN2

4

CBYP

8

POR

7

NC

5

CPOR

6

GND

C1 C2 C3

C4 C5

R1

Vout 2 OK

Vout2 too low

Vout 1

Vout 2

RESET

(200ms delay, C3 = 0.01µF)

C1, C4, C5: 1μF X5R ceramic capacitor

C2: 0.01μF X5R ceramic capacitor

C3: 0.01μF X5R ceramic capacitor

R1: 100kΩ resistor, 5%

8

FN9220.2

May 8, 2006

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