ISPLSI1016EA データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI1016EA Datasheet PDF : 13 Pages
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Specifications ispLSI 1016EA
Internal Timing Parameters1
PARAM. #2
DESCRIPTION
-200
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tiobp 22 I/O Register Bypass
– 0.3 – 0.3 – 0.4 ns
tiolat 23 I/O Latch Delay
– 4.0 – 4.0 – 4.0 ns
tiosu 24 I/O Register Setup Time before Clock
3.0 – 3.0 – 3.4 – ns
tioh
25 I/O Register Hold Time after Clock
0.0 – 0.0 – 0.0 – ns
tioco
tior
tdin
GRP
tgrp1
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
29 GRP Delay, 1 GLB Load
– 4.0 – 4.6 – 5.0 ns
–
–
–
4.0 – 4.6 –
W 1.1 – 1.9 –
NE 1.3 – 1.7 –
5.0
2.2
2.1
ns
ns
ns
tgrp4 30 GRP Delay, 4 GLB Loads
R tgrp8 31 GRP Delay, 8 GLB Loads
O tgrp16 32 GRP Delay, 16 GLB Loads
F GLB
t4ptbpc 33 4 ProductTerm Bypass Path Delay (Combinatorial)
5 S t4ptbpr 34 4 Product Term Bypass Path Delay (Registered)
4A N t1ptxor 35 1 ProductTerm/XOR Path Delay
t20ptxor 36 20 Product Term/XOR Path Delay
H IG txoradj 37 XOR Adjacent Path Delay 3
C S tgbp 38 GLB Register Bypass Delay
E tgsu
39 GLB Register Setup Time before Clock
A tgh
40 GLB Register Hold Time after Clock
M D tgco
41 GLB Register Clock to Output Delay
p V tgro
is 5 tptre
42 GLB Register Reset to Output Delay
43 GLB Product Term Reset to Register Delay
– 1.5
– 1.7
– 2.1
– 1.7
– 1.8
– 1.9
– 1.9
– 1.9
– 0.6
0.2 –
1.0 –
– 1.4
– 3.8
– 2.5
–
–
–
–
–
–
–
–
–
0.3
3.5
–
–
–
1.9 –
2.1 –
2.5 –
3.4 –
3.1 –
3.6 –
3.6 –
3.6 –
1.2 –
– 1.4
– 4.0
1.4 –
4.9 –
3.8 –
2.3
2.5
2.9
4.9
4.9
4.3
4.3
4.3
2.1
–
–
1.7
5.0
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tptoe
tptck
tgfb
ORP
44 GLB Product Term Output Enable to I/O Cell Delay
45 GLB Product Term Clock Delay
USE 46 GLB Feedback Delay
– 2.1 – 5.7 – 7.2 ns
1.5 2.5 2.8 3.9 3.5 4.7 ns
– 0.0 – 0.3 – 0.3 ns
torp
47 ORP Delay
– 0.8 – 1.3 – 1.4 ns
torpbp 48 ORP Bypass Delay
– 0.1 – 0.2 – 0.4 ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1016EA
v.2.6
7
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