ISPLSI2032VE データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI2032VE Datasheet PDF : 15 Pages
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Specifications ispLSI 2032VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 3
COND.
#
DESCRIPTION1
-180
-135
-110
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 5.0 – 7.5 – 10.0 ns
tpd2
A 2 Data Propagation Delay
– 7.5 – 10.0 – 13.0 ns
fmax
A
3 Clock Frequency with Internal Feedback 2
180 – 135 – 111 – MHz
fmax (Ext.)
fmax (Tog.)
–
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
) tco1
118
–
100
– 77.0 –
MHz
– 5 Clock Frequency, Max. Toggle
200 – 167 – 125 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 3.0 – 4.0 – 5.5 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 4.0 – 4.5 – 5.0 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 – 0.0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clock
4.0 – 5.5 – 7.5 – ns
tco2
A 10 GLB Reg. Clock to Output Delay
– 5.0 – 5.5 – 6.5 ns
th2
– 11 GLB Reg. Hold Time after Clock
0.0 – 0.0 – 0.0 – ns
tr1
A 12 Ext. Reset Pin to Output Delay, ORP Bypass
– 6.0 – 9.0 – 12.5 ns
trw1
– 13 Ext. Reset Pulse Duration
4.0 – 5.0 – 6.5 – ns
tptoeen
B 14 Input to Output Enable
– 10.0 – 12.0 – 14.5 ns
tptoedis
C 15 Input to Output Disable
– 10.0 – 12.0 – 14.5 ns
tgoeen
B 16 Global OE Output Enable
– 5.0 – 6.0 – 7.0 ns
tgoedis
C 17 Global OE Output Disable
– 5.0 – 6.0 – 7.0 ns
twh
– 18 External Synchronous Clock Pulse Duration, High 2.5 – 3.0 – 4.0 – ns
twl
– 19 External Synchronous Clock Pulse Duration, Low 2.5 – 3.0 – 4.0 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2032VE
v.0.1
6
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