ISPLSI2064V-80LJ44 データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI2064V-80LJ44 Datasheet PDF : 14 Pages
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Specifications ispLSI 2064V
Pin Description
NAME
44-PIN PLCC
PIN NUMBERS
44-PIN TQFP
PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 3
15, 16, 17, 18, 9, 10, 11, 12, Input/Output Pins — These are the general purpose I/O pins
I/O 4 - I/O 7
19, 20, 21, 22, 13, 14, 15, 16, used by the logic array.
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 3
GOE 1/Y0
RESET/Y1
25, 26, 27, 28, 19, 20, 21, 22,
29,
37,
41,
3,
7,
2
11
30,
38,
42,
4,
8,
31, 32, 23,
39, 40, 31,
43, 44, 35,
5, 6, 41,
9, 10 1,
40
5
24,
32,
36,
42,
2,
25,
33,
37,
43,
3,
26,
34,
38,
44,
4
NS This pin performs one of two functions. It can be programmed to
IG function as a Global Output Enable pin or a Dedicted Input pin.
This pin performs one of two functions. It can be programmed
S to function as a Global Output Enable or a Dedicated Clock
input. This clock input is connected to one of the clock inputs of
DE all the GLBs on the device.
35
29
This pin performs one of two functions. It can be programmed
ispEN
13
7
to function as a Dedicated Clock Input that is brought into the
Clock Distribution Network and can optionally be routed to any
W GLB and/or I/O cell on the device, or as an Active Low (0)
Reset pin which resets all of the GLB and I/O registers in the
E device.
N Input — Dedicated in-system programming enable input pin.
TDI/IN 0
TMS/IN 2
TDO/IN 1
TCK/Y2
GND
VCC
14
36
24
33
LSI 1, 23
isp12, 34
8
30
4VE 18
20627
17, 39
6, 28
This pin is brought low to enable the programming mode. The
TMS, TDI, TDO and TCK controls become active.
R Input — This pin performs two functions. When ispEN is logic
low, it functions as an input pin to load programming data into
Othe device. TDI/IN 0 also is used as one of the two control pins
Ffor the ISP state machine. When ispEN is high, it functions as a
dedicated input pin.
Input — This pin performs two functions. When ispEN is logic
low, it functions as a pin to control the operation of the ISP
state machine. When ispEN is high, it functions as a dedicated
input pin.
Output/Input — This pin performs two functions. When ispEN is
logic low, it functions as an output pin to read serial shift register
data. When ispEN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic
low, it functions as a clock pin for the Serial Shift Register.
When ispEN is high, it functions as a dedicated clock input. This
clock input is brought into the Clock Distribution Network, and
can optionally be routed to any GLB and/or I/O cell on the
device.
Ground (GND)
Vcc
USE
Table 2-0002B/2064V
10
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