ISPLSI2064V-80LJ44 データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI2064V-80LJ44

3.3V High Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI 2064V

Functional Block Diagram

Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions)

Megablock

I/O 0

I/O 1

A0

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

A1

I/O 7

I/O 8

I/O 9

I/O 10

A2

I/O 11

Input Bus

Output Routing Pool (ORP)

B7

B6

B5

B4

Generic Logic

Blocks (GLBs)

Megablock

Global Routing Pool

(GRP)

I/O 47

I/O 0

B3

I/O 46

I/O 1

A0

I/O 45

I/O 2

I/O 44

I/O 3

I/O 43

I/O 42

B2

I/O 41

A1

I/O 40

I/O 39

I/O 38

B1

I/O 37

A2

I/O 36

Input Bus

Output Routing Pool (ORP)

S B7

B6

B5

B4

Generic Logic

Blocks (GLBs)

SIGN Global Routing Pool

DE (GRP)

I/O 23

B3

I/O 22

I/O 21

I/O 20

B2

B1

I/O 12

I/O 13

I/O 14

I/O 15

TDI/IN 0

TMS/IN 1

RESET

ispEN

A3

B0

A4

A5

A6

A7

Output Routing Pool (ORP)

Input Bus

I/O 35

I/O 34

I/O 33

I/O 32

TCK/IN 3

TDO/IN 2

I/O 4

I/O 5

I/O 6

I/O 7

TDI/IN 0

TDO/IN 1

ispEN

A3

W A4

A5

A6

EOutput Routing Pool (ORP)

N Input Bus

A7

B0

I/O 19

I/O 18

I/O 17

I/O 16

GOE0/IN 3

TMS/IN 2

0139B/2064V

The 64-I/O 2064V contains 64 I/O cells, while the 32-I/O

0139B/2064V.32IO

FOR Y2) or an asynchronous clock can be selected on a GLB

version contains 32 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

E grammed to be a combinatorial input, output or

V bi-directional I/O pin with 3-state control. The signal

4 levels are TTL compatible voltages and the output drivers

can source 4 mA or sink 8 mA. Each output can be

6 programmed independently for fast or slow output slew

0 rate to minimize overall output switching noise. Device

2 pins can be safely driven to 5-Volt signal levels to support

I mixed-voltage systems.

S Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and

L two or one ORPs are connected together to make a

p Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 32 or 16 universal I/O cells by

is two or one ORPs. Each ispLSI 2064V device contains

two Megablocks.

E The GRP has as its inputs, the outputs from all of the

S GLBs and all of the inputs from the bi-directional I/O cells.

U All of these signals are made available to the inputs of the

basis. The asynchronous or Product Term clock can be

generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2064V are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. When this fuse is erased (JEDEC “1”),

the output is configured as a totem-pole output. When

this fuse is programmed (JEDEC “0”), the output is

configured as an open-drain. The default configuration

when the device is in bulk erased state is totem-pole

configuration. The open-drain/totem-pole option is se-

lectable through the ispDesignEXPERT software tools.

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2064V device are selected using the

dedicated clock pins. Three dedicated clock pins (Y0, Y1,

2

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