ISPLSI2064V-60LJ84I データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI2064V-60LJ84I Datasheet PDF : 14 Pages
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Specifications ispLSI 2064V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-100
-80
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
A
A
–
–
–
A
–
–
–
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback 3
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
) tco1
5 Clock Frequency, Max. Toggle
6 GLB Reg. Setup Time before Clock, 4 PT Bypass
7 GLB Reg. Clock to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
– 12.0
102 –
83.3 –
125 –
5.5 –
– 5.0
0.0 –
7.0 –
– 6.3
– 15.0 – 20.0
S 80.0 – 61.7 –
64.5 – 51.3 –
N 100 – 71.4 –
IG 7.0 – 9.0 –
– 6.5 – 8.5
S 0.0 – 0.0 –
E 9.0 – 11.0 –
D– 7.5 – 9.5
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
th2
tr1
trw1
tptoeen
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
0.0 – 0.0
W – 12.0 –
5.0 – 7.0
NE– 13.0 –
–
14.0
–
15.0
0.0
–
8.0
–
–
16.0
–
18.0
ns
ns
ns
ns
tptoedis
tgoeen
R tgoedis
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
– 13.0
– 7.5
– 7.5
O twh
– 18 External Synchronous Clock Pulse Duration, High 4.0 –
F twl
– 19 External Synchronous Clock Pulse Duration, Low 4.0 –
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
E 2. Refer to Timing Model in this data sheet for further details.
V 3. Standard 16-bit counter using GRP feedback.
ispLSI 2064 4. Reference Switching Test Conditions section.
–
–
–
5.0
5.0
15.0
10.0
10.0
–
–
–
–
–
7.0
7.0
18.0 ns
12.0 ns
12.0 ns
– ns
– ns
Table 2-0030/2064V
USE
5
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