ISPLSI2064V-60LJ84I データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI2064V-60LJ84I Datasheet PDF : 14 Pages
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Specifications ispLSI 2064V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
-100
-80
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tio
tdin
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
20 Input Buffer Delay
21 Dedicated Input Delay
22 GRP Delay
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
–
–
–
–
0.2
0.6
0.7
4.6
6.0
6.7
– 0.4 – 0.6 ns
S – 1.3 – 1.4 ns
N – 1.2 – 2.1 ns
IG – 5.8
S – 7.5
DE – 9.2
– 9.6 ns
– 10.3 ns
– 12.3 ns
t20ptxor
txoradj
W tgbp
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
E tgsu
N tgh
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
tgco
31 GLB Register Clock to Output Delay
R tgro
O tptre
F tptoe
tptck
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
E ORP
V torp
4 torpbp
36 ORP Delay
37 ORP Bypass Delay
6 Outputs
0 tob
2 tsl
I toen
S todis
L tgoe
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
p Clocks
is tgy0
tgy1/2
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
E Global Reset
S tgr
45 Global Reset to GLB
U 1. Internal Timing Parameters are not tested and are for reference only.
– 7.5 –
– 8.5 –
– 0.3 –
0.1 – 0.2
3.8 – 5.4
– 1.5 –
– 2.2 –
– 3.8 –
– 7.2 –
3.0 4.4 3.8
– 1.4 –
– 0.1 –
– 1.9 –
– 11.9 –
– 4.9 –
– 4.9 –
– 2.6 –
1.5 1.5 2.3
1.5 1.5 2.3
– 6.5 –
9.5
11.3
0.3
–
–
1.6
2.5
5.6
8.5
5.6
1.4
0.4
2.2
12.2
4.9
4.9
5.1
2.3
2.3
7.9
–
–
–
0.2
8.0
–
–
–
–
6.5
–
–
–
–
–
–
–
4.2
4.2
–
12.3 ns
14.4 ns
1.3 ns
– ns
– ns
1.6 ns
2.8 ns
9.3 ns
10.4 ns
9.3 ns
1.5 ns
0.5 ns
2.2 ns
12.2 ns
4.9 ns
4.9 ns
7.1 ns
4.2 ns
4.2 ns
9.5 ns
Table 2-0036/2064V
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
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