ISPLSI2064V-60LJ84I データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI2064V-60LJ84I

3.3V High Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI 2064V

ispLSI 2064V Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Ded. In

#21

Comb 4 PT Bypass #23

I/O Pin

(Input)

I/O Delay

#20

Reset

GRP

#22

#45

Reg 4 PT Bypass

#24

20 PT

XOR Delays

#25, 26, 27

GLB Reg Bypass

#28

GLB Reg

Delay

D

Q

RST

#29, 30,

31, 32

Control RE

PTs OE

ORP Bypass

#37

S ORP

Delay

DESIGN #36

#38,

39

I/O Pin

(Output)

Y0,1,2

GOE 0,1

#43, 44

#42

#33, 34, CK

35

NEW

#40, 41

0491/2064

R Derivations of tsu, th and tco from the Product Term Clock1

tsu

= Logic + Reg su - Clock (min)

FO = (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

4.6 ns

E th

4V 0.7 ns

6 tco

I 20 10.1 ns

= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

= (0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)

= Clock (max) + Reg h - Logic

= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

= (0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)

= Clock (max) + Reg co + Output

= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#20 + #22 + #35) + (#31) + (#36 + #38)

= (0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)

S Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.

ispL Table 2-0042/2064V

USE

7

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