ISPLSI2064V-80LJ44 データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI2064V-80LJ44

3.3V High Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI 2064V

Pin Description

NAME

84-PIN PLCC

PIN NUMBERS

100-PIN TQFP

PIN NUMBERS

DESCRIPTION

I/O 0 - I/O 3

26, 27, 28, 29, 17, 18, 19, 20, Input/Output Pins — These are the general purpose I/O pins

I/O 4 - I/O 7

30, 31, 32, 33, 22, 23, 24, 26, used by the logic array.

I/O 8 - I/O 11

I/O 12 - I/O 15

I/O 16 - I/O 19

I/O 20 - I/O 23

I/O 24 - I/O 27

I/O 28 - I/O 31

I/O 32 - I/O 35

I/O 36 - I/O 39

I/O 40 - I/O 43

I/O 44 - I/O 47

I/O 48 - I/O 51

I/O 52 - I/O 55

I/O 56 - I/O 59

I/O 60 - I/O 63

34, 35, 36, 37, 27, 28, 29, 30,

38, 39, 40, 41, 32, 33, 34, 35,

45, 46, 47, 48, 40, 41, 42, 43,

49, 50, 51, 52, 45, 46, 47, 48,

53, 54, 55, 56, 49, 51, 52, 53,

57, 58, 59, 60, 55, 56, 57, 58,

68, 69, 70, 71, 67, 68, 69, 70,

72, 73, 74, 75, 72, 73, 74, 76,

76, 77, 78, 79, 77, 78, 79, 80,

80, 81, 82, 83, 82, 83, 84, 85,

3, 4

5, 6, 90, 91, 92, 93,

7, 8, 9, 10, 95, 96, 97, 98,

11, 12, 13, 14, 99, 1, 2, 3

15 16, 17, 18 5, 6, 7, 8

DESIGNS

GOE 0, GOE 1

Y0, Y1, Y2

RESET

ispEN

TDI/IN 0

TMS/IN 1

TDO/IN 2

TCK/IN 3

GND

VCC

NC1

64, 22

19, 67, 62

20

24

62, 13

10, 65, 60

11

15

Global Output Enable Input Pins

Dedicated Clock input. This clock input is connected to one of the

W clock inputs of all the GLBs in the device.

E Active Low (0) Reset pin which resets all registers in the device.

N Input — Dedicated in-system programming enable input pin.

25

16

This pin is brought low to enable the programming mode. The

TMS, TDI, TDO and TCK controls become active.

R Input — This pin performs two functions. When ispEN is logic

low, it functions as an input pin to load programming data into the

Odevice. TDI/IN 0 also is used as one of the two control pins for the

FISP state machine. When ispEN is high, it functions as a

dedicated input pin.

E 43

37

Input — This pin performs two functions. When ispEN is logic low,

it functions as a pin to control the operation of the ISP state

V machine. When ispEN is high, it functions as a dedicated input

pin.

4 1

87

Output/Input — This pin performs two functions. When ispEN is

6 logic low, it functions as an output pin to read serial shift register

0 data. When ispEN is high, it functions as a dedicated input pin.

2 61

59

Input — This pin performs two functions. When ispEN is logic

low, it functions as a clock pin for the Serial Shift Register. When

I ispEN is high, it functions as a dedicated input pin.

S 23, 44, 63, 84 14, 39, 61, 86 Ground (GND)

L 2, 21, 42, 65 12, 36, 63, 89 Vcc

p66

4, 9, 21, 25, No Connect.

is 31, 38, 44, 50,

54, 64,

75, 81

100

66, 71,

88, 94,

USE 1. NC pins are not to be connected to any active signals, VCC or GND.

Table 2-0002A/2064V

9

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