ISPLSI5256VA データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI5256VA

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5256VA

Functional Block Diagram

Figure 1. ispLSI 5256VA Functional Block Diagram (272 BGA Option)

VCCIO

1I/O 0 / TOE

I/O 1

I/O 2

I/O 3

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 44

I/O 45

I/O 46

I/O 47

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Global Routing Pool

(GRP)

Boundary

Scan

Interface

TDI

TDO

I/O 143

I/O 142

I/O 141

I/O 140

I/O 123

I/O 122

I/O 121

I/O 120

I/O 119

I/O 118

I/O 117

I/O 116

I/O 99

I/O 98

I/O 97

I/O 96

GSET/GRST

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is

determined by the package type used (see table below).

Package Type

208 PQFP

208 fpBGA

272 BGA

Multplexed Signals

I/O 89 / CLK2 I/O 98 / CLK3

I/O 89 / CLK2 I/O 98 / CLK3

I/O 119 / CLK2 I/O 131 / CLK3

I/O 0 / TOE

I/O 0 / TOE

I/O 0 / TOE

2

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