ISPLSI5256VE データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI5256VE

In-System Programmable 3.3V SuperWIDE™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 5256VE

Internal Timing Parameters

Over Recommended Operating Conditions

PARAMETER

DESCRIPTION

In/Out Delays

tin

Input Buffer Delay

tgclk_in

Global Clock Buffer Input Delay (clk0)

trst

Global Reset Pin Delay

tgoe

Global OE Pin Delay

tbuf

Output Buffer Delay

ten

Output Enable Delay

tdis

Output Disable Delay

-165

-125

-100

-80

MIN MAX MIN MAX MIN MAX MIN MAX UNIT

– 0.6 – 1.3 – 2.3 – 2.3 ns

– 0.7 – 1.3 – 1.8 – 1.8 ns

– 4.9 – 6.6 – 7.1 – 7.1 ns

– 3.2 – 3.9 – 5.9 – 7.4 ns

– 1.9 – 2.2 – 2.7 – 3.7 ns

– 1.3 – 1.6 – 1.6 – 1.6 ns

– 1.3 – 1.6 – 1.6 – 1.6 ns

Routing/GLB Delays

troute

GRP and Logic Delay

tpdb

5-pt Bypass Propagation Delay

tpdi

Combinatorial Propagation Delay

tptsa

Product Term Sharing Array

tfbk

Internal Feedback Delay

tinreg

Input Buffer to Macrocell Register Delay

– 3.2 – 3.6 – 4.0 – 4.5 ns

– 0.3 – 0.4 – 1.0 – 1.5 ns

– 0.0 – 0.0 – 0.0 – 0.0 ns

– 1.8 – 2.4 – 3.0 – 4.5 ns

– 0.0 – 0.0 – 0.0 – 0.5 ns

– 2.0 – 2.5 – 2.5 – 3.5 ns

Register/Latch Delays

ts

Register Setup Time

0.6 – 1.0 – 1.5 – 1.5 –

ns

ts_pt

Register Setup Time (Product Term Clock)

0.6 – 1.0 – 1.5 – 1.5 –

ns

th

Register Hold Time

2.4 – 3.0 – 4.0 – 5.0 –

ns

tcoi

Register Clock to GLB Output Delay

– 0.4 – 1.0 – 1.5 – 1.5 ns

tsl

Latch Setup Time

0.6 – 1.0 – 1.5 – 1.5 –

ns

thl

Latch Hold Time

2.4 – 3.0 – 4.0 – 5.0 –

ns

tgoi

Latch Gate to GLB Output Delay

– 0.4 – 1.0 – 1.5 – 1.5 ns

tpdli

GLB Latch propagation Delay

– 1.0 – 1.5 – 2.0 – 2.5 ns

tces

Clock Enable Setup Time

4.1 – 4.3 – 5.3 – 6.3 –

ns

tceh

Clock Enable Hold Time

0.9 – 1.7 – 2.7 – 3.7 –

ns

tsri

Asynchronous Set/Reset to GLB Output Delay – 1.2 – 1.2 – 1.7 – 2.2 ns

tsrr

Asynchronous Set/Reset Recovery Time

0.8 – 1.2 – 1.2 – 2.2 –

ns

Control Delays

tptclk

Macrocell PT Clock Delay

– 0.4 – 0.4 – 0.5 – 0.5 ns

tbclk

Block PT Clock Delay

– 1.4 – 1.9 – 2.5 – 2.5 ns

tptsr

Macrocell PT Set/Reset Delay

– 2.1 – 3.7 – 4.8 – 4.8 ns

tbsr

Block PT Set/Reset Delay

– 3.1 – 5.7 – 6.8 – 6.8 ns

tptoe

Macrocell PT OE Delay

– 1.9 – 2.0 – 2.1 – 3.6 ns

tgptoe

Global PT OE Delay

– 6.9 – 7.5 – 7.6 – 8.6 ns

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet Timing v.2.0

for further details.

15

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