IXC1100 データシートの表示（PDF） - Intel

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IXC1100

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Intel 

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Table 2.

Terminology and Acronyms (Continued)

Acronym/

Terminology

DDR

DES

DMA

DSP

E1

FIFO

GCI

GPIO

HDLC

HPI

HSS

LSb

LSB

MAC

MDIO

MII

MMU

MSb

MSB

NPE

PCI

PHY

Reserved

RX

SRAM

SDRAM

T1

TX

UART

USB

UTOPIA

WAN

Description

Double Data Rate

Data-Encryption Standard

Direct Memory Access

Digital Signal Processor

Euro 1 trunk line

First In First Out

General Circuit Interface

General-purpose input/output

High-level Data Link Control

(Texas Instruments*) Host Port Interfaces

High-Speed Serial (port)

Least-Significant bit

Least-Significant Byte

Media Access Controller

Management Data Input/Output

Media-Independent Interface

Memory Management Unit

Most-Significant bit

Most-Significant Byte

Network Processor Engine

Peripheral Component Interconnect

Physical Layer (Layer 1) Interface

A field that may be used by an implementation. Software should not modify reserved fields

or depend on any values in reserved fields.

Receive (HSS is receiving from off-chip)

Static Random Access Memory

Synchronous Dynamic Random Access Memory

Type 1 trunk line

Transmit (HSS is transmitting off-chip)

Universal Asynchronous Receiver-Transmitter

Universal Serial Bus

Universal Test and Operations PHY Interface for ATM

Wide Area Network

March 2005

10

Document Number: 252479, Revision: 005

Datasheet

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