K6T0808C1D-B データシートの表示（PDF） - Samsung
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K6T0808C1D-B Datasheet PDF : 9 Pages
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K6T0808C1D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
WE
Data in
Data out
tAS(3)
Data Undefined
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
tWHZ
tDW
tDH
Data Valid
tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
tAS(3)
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
WE
Data in
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS
GND
CS≥VCC - 0.2V
Revision 1.01
November 1997
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