K6X4016T3F-TB85 データシートの表示（PDF） - Samsung

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K6X4016T3F-TB85

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

Samsung 

K6X4016T3F Family

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

Address

CS

UB, LB

WE

Data in

tAS(3)

tWC

tCW(2)

tAW

tBW

tWP(1)

tWR(4)

tDW

tDH

Data Valid

CMOS SRAM

Data out

High-Z

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

VCC

2.7V

tSDR

Data Retention Mode

tRDR

2.2V

VDR

CS

GND

CS≥VCC - 0.2V

8

Revision 1.0

August 2003

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