PDSP16256B0(1998) データシートの表示（PDF） - Mitel Networks
部品番号
コンポーネント説明
メーカー
PDSP16256B0 Datasheet PDF : 24 Pages
| |||
128 TAP
127
64 TAP
127
32 TAP
127
PDSP16256
16 TAP
127
NO SWAP
POSSIBLE
0
64 TAP
127
FILTER B
NO SWAP
POSSIBLE
64
63
FILTER A
NO SWAP
POSSIBLE
0
UPPER
BANK
NOT USED
64
64
63
63
LOWER
BANK
UPPER
BANK
32
31
LOWER
BANK
0
0
(a) Single Filters
32 TAP
127
16 TAP
127
B UPPER
BANK
96
95
NOT USED
A UPPER
BANK
64
63
B LOWER
BANK
32
31
A LOWER
BANK
0
64
63
B UPPER
48
47
A UPPER
32
31
B LOWER
16
15
A LOWER
0
(b) Dual Filters
NOT USED
32
31
UPPER
16
BANK
15
LOWER
0
BANK
8 TAP
127
NOT USED
32
31
B UPPER
A UPPER
B LOWER
0
A LOWER
Fig. 14 Coefficient memory map
FILTER CONTROL
Two control modes are available selected by input signal
FRUN. In EPROM load mode, when FRUN is tied high the
device will commence operation once the coefficients have
been loaded. The CLKOP signal indicates when new input
data is required and that new results are available, see Fig. 7.
In both EPROM and remote master load modes, when FRUN
is tied low filter operation will not commence until a high has
been detected on signal FEN. This mode allows synchronisa-
tion to an existing data stream. FEN should be taken high when
the first valid data sample is available so that both are read into
the device on the next SCLK rising edge.
During device reset RES must be held low for a minimum
of 16 SCLK cycles. After a reset the control register returns to
its default state of 8C80 HEX. This places the device into the
following mode :
q Single filter
q Sample rate equal to the clock rate
q Non-decimating
q A single device (Not in a cascade chain)
q Bank swap selected by bit in the control register
COEFFICIENT BANK SWAP
A Bank Swap feature is provided which allows all coeffi-
cients to be simultaneously replaced with a different set. A bit
in the Control Register (CR7) allows the swap to be controlled
by either input signal SWAP or Control Register bit (CR6). The
latter is useful if the device is controlled by a microprocessor,
when driving a separate pin would entail additional address
decoding logic and an external latch.
If SWAP or bit CR6 is low, the coefficients used will be those
loaded into the lower banks illustrated in Fig. 14. When the
SWAP or CR6 is high, the upper banks are used.
The actual swap will occur when the next sampling clock
active going transition occurs. This can be up to seven system
clocks later than the swap transition, and is filter length
dependent. The first valid filtered output will then occur after
the pipeline latencies given in Tables 3 and 4.
LOADING COEFFICIENTS
When the device is to operate in a stand alone application
then the coefficients can be down loaded as a complete set
from a previously programmed EPROM. Alternatively if the
11
Share Link: 