KM68512A データシートの表示（PDF） - Samsung
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KM68512A Datasheet PDF : 9 Pages
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KM68512A Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
CL1)
Output load(see right) : CL=100pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO1, tCO2
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min
Max
Min
Max
55
-
70
-
-
55
-
70
-
55
-
70
-
25
-
35
10
-
10
-
5
-
5
-
0
20
0
25
0
20
0
25
10
-
10
-
55
-
70
-
45
-
60
-
0
-
0
-
45
-
60
-
40
-
50
-
0
-
0
-
0
20
0
25
25
-
30
-
0
-
0
-
5
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
KM68512AL/L-L
IDR
KM68512ALI/LI-L
tSDR
tRDR
Test Condition
CS11)≥Vcc-0.2V
Vcc=3.0V CS1≥Vcc-0.2V
CS2≥Vcc-0.2V or CS2≤0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
See data retention waveform
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled).
Min Typ Max Unit
2.0
-
5.5
V
-
1
50
-
0.5
10
µA
-
-
50
-
-
25
0
-
-
ms
5
-
-
5
Revision 4.0
January 1997
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