KS0068B-00 データシートの表示（PDF） - Samsung
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KS0068B-00 Datasheet PDF : 22 Pages
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KS0068B
16COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Î MAXIMUM ABSOLUTE LIMIT (Ta=25 )
Characteristic
Symbol
Value
Operating Voltage
VDD
-0.3~+7.0
Driver Supply Voltage
VLCD
VDD-11.5~VDD+0.3
Input Voltage
VIN
-0.3 ~ VDD+0.3
Power Dissipation
PD
500
Operating Temperature
TOPR
-30~+85
Storage Temperature
TSTG
-55~+125
~ Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5)
Unit
V
V
V
mÎÎW
ELECTRICAL CHARACTERISTICS
ä Î DC Characteristics (VDD=+5V 10%, VSS=0V, Ta=-30 ~ +85 )
Characteristic
Symbol
Test condition
Min Typ Max Unit Applicable Pin
Operating Voltage
Operating Current (*1)
VDD
-
4.5
-
5.5
V
IDD1
Ceramic resonator
-
0.65 0.9 mA
fosc=250KHz
IDD2
Resistor oscillation
-
external clock operation
0.45 0.7
fosc=270KHz
Input Voltage 1
High
VIH1
-
2.2
-
VDD
V
E, DB0-DB7,
Low
VIL1
-
-0.3
-
0.6
R/W, RS
Input Voltage 2
High
VIH2
-
VDD
-
VDD
-1.0
OSC1
Low
VIL2
-
-0.2
-
1.0
Output Voltage 1
Output Voltage 2
High
Low
High
Voltage Drop (*2)
Input Leakage Current
Low
COM
SEG
VOH1
VOL1
VOH2
VOL2
VdCOM
VdSEG
ILKG
IOH=-0.205mA
À IOL=1.2mA
IO=-40
À IO=40
IO=ä0.1mA
VIN=0 or VDD
2.4
-
-
-
-
0.4
DB0-DB7
0.9VDD
-
-
CLK1, CLK2,
M, D
-
-
0.1VDD
-
-
1
C1-C16
-
-
-1
-
1
1À
S1-S60
E
Input Low Current
IIN
VDD=5V (test pull up R) -50 -125 -250
RS,R/W
External Clock
Frequency(*3)
fEC
-
125 250 350 KHz
OSC1
Duty
Rise time
Fall time
Internal Clock Frequency(*3)
duty
tR
tF
fOSC1
< Rf=91K ä2%
45
50
55
%
-
-
¶ 0.2
-
-
¶ 0.2
190 270 350 KHz OSC1, OSC2
Ceramic Resonator OSC Frequency fOSC2
(*3)
245 250 255
LCD driving voltage(*4)
VLCD1
VDD-V5
1/5 bias
3.0
VLCD2
1/6 bias
3.0
-
10.0 V
-
10.0
V1-V5
Note: *1) Applies to the current value flown in terminal VDD when power is input as follows; VDD=5V, GND=0V, V1=3.4V,
V2=1.8V, V3=0.2V, V4=-1.4V and V5=-3V.
*2) Applied to the voltage drop occuring from terminals VDD, V1, V4 and V5 to each common terminal (C1-C16) when
0.1mA is flown in or out to and from all COM and SEG terminals, and also to voltage drop occuring from terminals
VDD, V2, V3 and V5 to each SEG terminal (S1-S60). When the output level is at VDD, V1 or V2 level, 0.1mA is flown
out, while 0.1mA flow in when the output level is at V3, V4 or V5 level. This occurs when 5V or -5V is input to VDD, V1
and V3 or to V2, V4, and V5 respectively.
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