KS0073 データシートの表示（PDF） - Samsung

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KS0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Samsung 

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

FUNCTION DESCRIPTION

System Interface

This chip has all three kinds of interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit)

are selected by IM input, and 4-bit bus and 8-bit bus are selected by DL bit in the instruction register. During read

or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The

data register(DR) is used as temporary data storage place for being written into or read from

DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,

reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next

DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the

data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only

to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use

RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low").

Table 2. Various Kinds of Operations according to RS and R/W Bits

RS

R/W

Operation

L

L

Instruction Write operation (MPU writes Instruction code into IR)

L

H

Read Busy flag(DB7) and address counter (DB0 – DB6)

H

L

Data Write operation (MPU writes data into DR)

H

H

Data Read operation (MPU reads data from DR)

Busy Flag (BF)

When BF = "High", it indicates that the internal operation is being processed. So during this time the next

instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),

through DB7. Before executing the next instruction, be sure that BF is not High.

Display Data RAM (DDRAM)

DDRAM stores display data of maximum 80 × 8 bits (80 characters). DDRAM address is set in the address

counter (AC) as a hexadecimal number. (refer to Figure 1.)

MSB

LSB

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Figure 1. DDRAM Address

11

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