TDA1546T データシートの表示（PDF） - Philips Electronics

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TDA1546T

Bitstream Continuous Calibration DAC with digital sound processing (BCC-DAC)

Philips Electronics 

Philips Semiconductors

Preliminary specification

Bitstream Continuous Calibration DAC with

digital sound processing (BCC-DAC)

TDA1546T

Data bits 0 to 1 indicate the type of the subsequent data

transfer as shown below in Table 2. The direction of the

channel status and user data transfers depends on the

transmit/receive mode.

Table 2 Selection of data exchange

BIT 1(1) BIT 0

TRANSFER

X

0

data to TDA1546T

X

1

data from

TDA1546T

Note

1. Where X = don't care.

DIRECTION

input

output

Data bits 2 to 7 represent a 6-bit device address, with bit 7

being the MSB and bit 2 the LSB. The address of the

TDA1546T is 000100 (bit 7 to bit 2). In the event that the

TDA1546T receives a different address, it immediately

3-states the L3DATA pin and deselects its microcontroller

interface logic. A dummy address of 000000 is defined for

the deselection of all devices that are connected to the

serial microcontroller bus.

7.3.2 DATA TRANSFER MODE

The selection performed in the address mode remains

active during subsequent data transfers, until the

TDA1546T receives a new address command. The

fundamental timing of data transfers is shown in Fig.7,

where L3DATA denotes the data from the TDA1546T to

the microcontroller (L3DATA write). The timing for the

opposite direction is essentially the same as in the address

mode (L3DATA read). The maximum input clock and data

rate is 64fs (or 32fs when in the double-speed mode).

Fig.7 Timing for data transfer mode.

All transfers are bytewise, i.e. they are based on groups of

8 bits. Data will be stored in the TDA1546T after the eighth

bit of a byte has been received.

A multi-byte transfer is illustrated in Fig.8. The definition of

the L3 protocol allows for a so-called “halt” mode, as some

devices which are expected to connect to the same

microcontroller bus lines may require an indication of when

8 bits have been transferred. This halt mode option is

implemented in the TDA1546T, meaning that subsequent

byte transfers must be separated by a period identified as

halt mode. A halt mode period is characterized by the

following conditions:

L3MODE = LOW, L3DATA = 3-state and L3CLK = HIGH.

January 1995

11

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