SAA7206 データシートの表示（PDF） - Philips Electronics

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SAA7206

DVB compliant descrambler

Philips Electronics 

Philips Semiconductors

DVB compliant descrambler

Product specification

SAA7206H

7.1 MPEG-2 systems parsing

The descrambler receives data from a Forward Error

Correction (FEC) decoder (see Fig.5) in a digital TV

receiver, in the following input data format:

• 8 data bits via MIN7 to MIN0.

• A valid input data indicator signal (MDV), which is HIGH

for consecutive valid bytes and output by either a FEC

decoder or a descrambler. Consequently the

descrambler input data is allowed to have a ‘bursty’

nature.

• A transport packet error indicator (MB/MB) which is

HIGH for the duration of each 188 byte transport packet

in which the FEC decoder found more errors than it

could correct. The polarity (active HIGH or LOW) of the

error indicator is programmable [bit ‘Bad_polarity’

(see Table 10, address 0x0100)].

• A packet sync signal (MSYNC) which goes HIGH at the

start of the first byte of a transport packet. Only the rising

edge of MSYNC is used for synchronization, the exact

HIGH time of the signal is therefore irrelevant.

• A byte strobe signal (MBCLK; < 9 MHz) which indicates

consecutive data bytes in the input stream, in the non

9 MHz mode only [bit ‘9 MHz_interface’ = 0

(see Table 10, address 0x0100)]. MBCLK is used as an

enable signal, and transport stream input bytes are

sampled on its rising edges. If the input interface is

programmed to the 9 MHz mode

(‘9 MHz_interface’ = 1), the MBCLK signal is ignored

and bytes are latched on rising edges of the DCLK.

• A descrambler clock signal (DCLK; 9 MHz; duty cycle

range 30 to 55%) which is the processing clock for the

descrambler IC. If rising edges of this signal are used to

input data to the descrambler, the 9 MHz mode must be

programmed (bit ‘9 MHz_interface’ = 1, see Table 10,

address 0x0100).

The parser module in the descrambler parses transport

streams compliant to the MPEG-2 systems syntax.

MPEG-2 systems specifies a hierarchical two-level

multiplex (see Fig.6). The top hierarchical level is the

transport stream, consisting of relatively short (188 byte)

transport packets. Each transport packet consists of a

4 byte transport header, an optional adaptation field and a

payload. The transport header contains a 13-bit PID field.

The adaptation field may contain Program Clock

Reference (PCR) data and transport private data, among

others. Both transport header and optional adaptation

fields are parsed by the TS parser module.

The hierarchical multiplex level below the MPEG-2

transport stream is the packetized elementary stream.

The PES header is only parsed partially by the DVB

descrambler to locate its scrambling control bits. Parsing is

performed for all incoming transport packets, and the

parser is synchronized to a rising edge on its MSYNC

input. A microcontroller can compose a set of 6 PIDs by

programming the appropriate registers in the PID filter

bank within the descrambler.

These PIDs identify the packets of the streams that are to

be descrambled. All 13 bits of PID5 (see Table 10,

address 0x0205) can be individually enabled/disabled with

a mask of 13 bits (see Table 10, address 0x0209) to

enable multiple PID selection. The PIDs of PES scrambled

packets must be indicated by programming a logic 1 to the

corresponding bit of the ‘PIDi_is_pes’ word

(see Table 10, address 0x0206).

MPEG-2 multiplex fields which are related to CA

information, in so called sections, are parsed only partly.

CA sections containing for instance Entitlement

Management Messages (EMM) and Entitlement Control

Messages (ECM) etc. are retrieved from the stream and

stored in 256 byte buffers in the CA filter module. For the

selection of CA data, 18 additional PIDs and section

header information (table_id, address field, both with bit

masks) can be programmed. All 13 bits of PID filters

16 and 17 can be individually enabled/disabled with a

mask of 13 bits (see Table 10, addresses 0x03A6

and 0x03BA) to enable multiple PID selection for CA

messages. A microcontroller may access data in the

256 byte CA buffers (each filter has its own buffer thus

18 in total) for software based parsing and processing.

1996 Oct 09

10

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