SAA7206 データシートの表示（PDF） - Philips Electronics

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SAA7206

DVB compliant descrambler

Philips Electronics 

Philips Semiconductors

DVB compliant descrambler

Product specification

SAA7206H

4 QUICK REFERENCE DATA

SYMBOL

VDDD

VDDD(core)

Ptot

PARAMETER

digital supply voltage

digital supply voltage for core

total power dissipation

fclk

Tamb

clock frequency

operating ambient temperature

CONDITIONS

VDDD(core) = 3.3 V,

VDDD = 5 V, CL = 15 pF

duty cycle = 30 to 55%

MIN.

−

−

−

TYP.

−

−

−

MAX.

5.5

3.6

250

UNIT

V

V

mW

−

−

9

MHz

0

−

70

°C

5 BLOCK DIAGRAM

handbook, full pagewidth

18

TDI

19

TCK

20

TMS

46

TRST

TC1

TC0

61

60

TEST CONTROL BLOCK

FOR

BOUNDARY SCAN TEST

AND

SCAN TEST

MB/MB MBCLK

MIN7 to MIN0 MDV MSYNC

47 to 50, 44 45 43 59

53 to 56

TRANSPORT STREAMS

AND

AF PARSER

22 DCLK

62

POR

TDO

DAT7

to

DAT0

DCS

R/W

A1

A0

IRQ

VDDD(core)

VDDD1

to

VDDD9

37

7 to 9,

12 to 16

3

63

4

5

1

SAA7206

MICROCONTROLLER

INTERFACE

CONDITIONAL

ACCESS

FILTERS

PACKET

IDENTIFICATION

BANK

CONTROL

WORD

BANK

STREAM

DECIPHER

BLOCK

DECIPHER

36

6, 11, 21, 26,

32, 41, 51, 57, 64

2, 17, 23, 27,

33, 52, 58

10, 42

VSSD1 to VSSD7

VSSD1(core),

VSSD2(core)

OUTPUT

INTERFACE

40

24, 25,

28 to 31,

34, 35

38

39

MGG313

OE

DATO0

to

DATO7

DVO

SYNCO

1996 Oct 09

Fig.1 Block diagram.

4

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