KS8721BI(2003) データシートの表示（PDF） - Micrel
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KS8721BI Datasheet PDF : 32 Pages
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KS8721B/BT
Strapping Options(Note 1)
Pin Number
Pin Name Type(Note 2)
6,5,
PHYAD[4:1]/
Ipd/O
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
9
PCS_LPBK/
Ipd/O
RXDV
11
ISO/RXER
Ipd/O
21
RMII/COL
Ipd/O
22
RMII_BTB
Ipd/O
CRS
27
SPD100/
Ipu/O
No FEF/
LED1
28
DUPLEX/
Ipu/O
LED2
29
NWAYEN/
Ipu/O
LED3
30
PD#
Ipu
Micrel
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Note 1.
Note 2.
Strap-in is latched during power-up or reset.
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
August 2003
9
KS8721B/BT
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