SAA7205H データシートの表示（PDF） - Philips Electronics

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SAA7205H

MPEG-2 systems demultiplexer

Philips Electronics 

Philips Semiconductors

MPEG-2 systems demultiplexer

Preliminary specification

SAA7205H

7.4 Interfacing to the external descrambler

An optional external descrambler can be incorporated in a digital TV receiver in the configuration indicated in Fig.7.

In such a configuration the demultiplexer generates a 9 MHz, 33% duty cycle descrambler clock (DCLK) signal

(see Fig.5). A descrambler could use this clock signal for data processing and outputting data. In such a configuration

the demultiplexer input interface is set to 9 MHz mode (bit 9 MHz_interface = 1, address 0x0100, see Table 13).

handbook, full pagewidth

SYSTEM

MICROCONTROLLER

DEMODULATOR

AND

FORWARD ERROR

CORRECTOR

OPTIONAL

DESCRAMBLER

MPEG2

DEMULTIPLEXER

SAA7205H

DCLK (9 MHz)

VIDEO

DECODER

AUDIO

DECODER

TELETEXT

AND

H/S DATA

APPLICATIONS

MGG767

Fig.7 Digital TV receiver configuration including a descrambler.

1997 Jan 21

17

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