SAA7205H データシートの表示（PDF） - Philips Electronics

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SAA7205H

MPEG-2 systems demultiplexer

Philips Electronics 

Philips Semiconductors

MPEG-2 systems demultiplexer

Preliminary specification

SAA7205H

handbook, full pagewidth

GPO7 to GPO0 byte 187

GPST

GPSYNC

GPV

consecutive transport packet bytes

sync byte (0)

tCLKOH

tCLKOL

byte 1

bytes 2 to 187

MGG770

Fig.9 Signal constellation for general purpose interface (SAA7201 compatible).

7.7 Interfacing to a third party video decoder

Communication to a third party video decoder involves

merging both video packetized elementary stream (PES)

or elementary stream (ES) data and control data on the

same 8-bit bidirectional bus VO7 to VO0 (see Fig.10).

PES or ES (bit: ‘video_pes_esn’, address 0x050A, see

Table 13) data is filtered by the video data filter and is

passed to a 768 Byte video FIFO buffer (see Section

“Output buffering for audio and video”), in which it is stored

at byte clock frequency (9 MHz). The video PES or ES

stream is read from the FIFO at video data acquisition

clock frequency CLKP (equals 9 MHz = CCLKI/3, 67%

duty cycle, see Fig.10). However, CLKP is a gated clock

signal, which is frozen to logic 1 in case of control

exchange between the microcontroller and the video

decoder (⇒ VSEL = 0), or FIFO underflow (see Fig.10).

A bidirectional bus multiplexer (‘Merger’) is therefore

located at the output of the video FIFO. The timing

associated with the video output interface is illustrated in

Fig.11.

The third party video interface outputs clock and

synchronization references. The set of references consists

of a 13.5 MHz clock (CLK13.5, programmable phase, bit:

‘clk_13p5_pol’, address 0x050A, see Table 13), a CbREF

signal, “CCIR 601” compliant H, V, composite syncs, and

a field parity (EVEN/ODD) signal (both 50 Hz and 60 Hz,

bit: ‘ccir_50_60n’, address 0x050A, see Table 13).

The CbREF signal is locked to CCLKI and indicates

U samples in the UY/VY video decoder output.

To compensate for the delay in the decoding path, the

phase of CbREF (active LOW) is programmable as

illustrated in Fig.13 [bits: cb_ref_phase (1 to 0)], address

0x050A, see Table 13). The clock period immediately

following a COMSYNC falling edge in normal lines (equals

HSYNC falling edge) corresponds to counter position 0,

the clock period preceding the falling edge corresponds to

position 1727 (50 Hz), or 1715 (60 Hz),

1997 Jan 21

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